517     uint16_t low_count, high_count;  in _i2c_fm_timing_set()  local
520     high_count = (uint16_t)MEC_DIV_ROUND_UP(I2C_FM_SCL_MIN_HIGH_PERIOD_NS, core_clk_freq_ns);  in _i2c_fm_timing_set()
521     if(high_count < I3C_SCL_TIMING_COUNT_MIN) {  in _i2c_fm_timing_set()
522         high_count = I3C_SCL_TIMING_COUNT_MIN;  in _i2c_fm_timing_set()
531     timing_val = (high_count << 16) | low_count;  in _i2c_fm_timing_set()
680     uint32_t low_count, high_count;  in _i2c_fmp_timing_set()  local
683     high_count = (uint32_t)MEC_DIV_ROUND_UP(I2C_FMP_SCL_MIN_HIGH_PERIOD_NS, core_clk_freq_ns);  in _i2c_fmp_timing_set()
684     if(high_count < I3C_SCL_TIMING_COUNT_MIN) {  in _i2c_fmp_timing_set()
685         high_count = I3C_SCL_TIMING_COUNT_MIN;  in _i2c_fmp_timing_set()
694     timing_val = (high_count << 16) | low_count;  in _i2c_fmp_timing_set()
707     uint32_t low_count = 0, high_count = 0, base_count = 0;  in _i3c_push_pull_timing_set()  local
716     high_count = (uint32_t)MEC_DIV_ROUND_UP(base_count * i3c_freq_ns, I3C_SCL_12_5MHZ_PERIOD_NS);  in _i3c_push_pull_timing_set()
718     if(high_count < I3C_SCL_TIMING_COUNT_MIN) {  in _i3c_push_pull_timing_set()
719         high_count = I3C_SCL_TIMING_COUNT_MIN;  in _i3c_push_pull_timing_set()
722     low_count = high_count;  in _i3c_push_pull_timing_set()
725     timing_val = (high_count << 16) | low_count;  in _i3c_push_pull_timing_set()
736     sdr_ext_lcount = MEC_DIV_ROUND_UP(I3C_BUS_SDR4_SCL_PERIOD_NS, core_clk_freq_ns) - high_count;  in _i3c_push_pull_timing_set()
738     sdr_ext_lcount |= MEC_DIV_ROUND_UP(I3C_BUS_SDR3_SCL_PERIOD_NS, core_clk_freq_ns) - high_count;  in _i3c_push_pull_timing_set()
740     sdr_ext_lcount |= MEC_DIV_ROUND_UP(I3C_BUS_SDR2_SCL_PERIOD_NS, core_clk_freq_ns) - high_count;  in _i3c_push_pull_timing_set()
742     sdr_ext_lcount |= MEC_DIV_ROUND_UP(I3C_BUS_SDR1_SCL_PERIOD_NS, core_clk_freq_ns) - high_count;  in _i3c_push_pull_timing_set()
757     uint32_t low_count = 0, high_count = 0;  in _i3c_open_drain_timing_set()  local
760 …  high_count = (uint32_t)MEC_DIV_ROUND_UP(I3C_OPEN_DRAIN_SCL_MIN_HIGH_PERIOD_NS, core_clk_freq_ns);  in _i3c_open_drain_timing_set()
762     high_count = (uint32_t)MEC_DIV_ROUND_UP(high_count * i3c_freq_ns, I3C_SCL_12_5MHZ_PERIOD_NS);  in _i3c_open_drain_timing_set()
764     if(high_count < I3C_SCL_TIMING_COUNT_MIN) {  in _i3c_open_drain_timing_set()
765         high_count = I3C_SCL_TIMING_COUNT_MIN;  in _i3c_open_drain_timing_set()
777     timing_val = (high_count << 16) | low_count;  in _i3c_open_drain_timing_set()