Lines Matching refs:mec_i3c_ctx

13 struct mec_i3c_ctx {  struct
225 void MEC_HAL_I3C_Soft_Reset(struct mec_i3c_ctx *ctx);
227 void MEC_HAL_I3C_Controller_Clk_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,
230 void MEC_HAL_I3C_Controller_Clk_Cfg(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,
233 void MEC_HAL_I3C_Controller_Clk_I2C_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz);
235 void MEC_HAL_I3C_Target_Init(struct mec_i3c_ctx *ctx, uint32_t core_clk_rate_mhz,
238 void MEC_HAL_I3C_Controller_Interrupts_Init(struct mec_i3c_ctx *ctx);
240 void MEC_HAL_I3C_Thresholds_Init(struct mec_i3c_ctx *ctx);
242 void MEC_HAL_I3C_Thresholds_Response_buf_set(struct mec_i3c_ctx *ctx, uint8_t threshold);
244 void MEC_HAL_I3C_Host_Config(struct mec_i3c_ctx *ctx);
246 void MEC_HAL_I3C_Sec_Host_Config(struct mec_i3c_ctx *ctx);
248 void MEC_HAL_I3C_Enable(struct mec_i3c_ctx *ctx, uint8_t address, uint8_t config);
250 void MEC_HAL_I3C_DO_DAA(struct mec_i3c_ctx *ctx, uint8_t tgt_idx, uint8_t tgts_count,
253 void MEC_HAL_I3C_DO_CCC(struct mec_i3c_ctx *ctx, struct mec_i3c_DO_CCC *tgt, uint8_t *tid_xfer);
257 void MEC_HAL_I3C_Xfer_Error_Resume(struct mec_i3c_ctx *ctx);
259 void MEC_HAL_I3C_Xfer_Reset(struct mec_i3c_ctx *ctx);
261 void MEC_HAL_I3C_DAT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth);
263 void MEC_HAL_I3C_DCT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth);
265 void MEC_HAL_I3C_DCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t DCT_idx,
268 bool MEC_HAL_I3C_Is_Current_Role_Primary(struct mec_i3c_ctx *ctx);
270 bool MEC_HAL_I3C_Is_Current_Role_Master(struct mec_i3c_ctx *ctx);
272 bool MEC_HAL_I3C_Is_Current_Role_BusMaster(struct mec_i3c_ctx *ctx);
274 void MEC_HAL_I3C_DAT_DynamicAddrAssign_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start,
277 void MEC_HAL_I3C_DAT_DynamicAddr_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start,
280 void MEC_HAL_I3C_queue_depths_get(struct mec_i3c_ctx *ctx, uint8_t *tx_depth, uint8_t *rx_depth,
283 void MEC_HAL_I3C_DO_Xfer_Prep(struct mec_i3c_ctx *ctx, struct mec_i3c_dw_cmd *cmd,
286 void MEC_HAL_I3C_DO_Xfer(struct mec_i3c_ctx *ctx, struct mec_i3c_dw_cmd *tgt);
288 void MEC_HAL_I3C_IBI_SIR_Enable(struct mec_i3c_ctx *ctx, struct mec_i3c_IBI_SIR *ibi_sir_info,
291 void MEC_HAL_I3C_IBI_SIR_Disable(struct mec_i3c_ctx *ctx, struct mec_i3c_IBI_SIR *ibi_sir_info,
294 void MEC_HAL_I3C_TGT_PID_set(struct mec_i3c_ctx *ctx, uint64_t pid, bool pid_random);
296 bool MEC_HAL_I3C_TGT_is_dyn_addr_valid(struct mec_i3c_ctx *ctx);
298 uint8_t MEC_HAL_I3C_TGT_dyn_addr_get(struct mec_i3c_ctx *ctx);
300 void MEC_HAL_I3C_TGT_MRL_set(struct mec_i3c_ctx *ctx, uint16_t mrl);
302 void MEC_HAL_I3C_TGT_MWL_set(struct mec_i3c_ctx *ctx, uint16_t mwl);
304 void MEC_HAL_I3C_TGT_MXDS_set(struct mec_i3c_ctx *ctx,
310 int MEC_HAL_I3C_TGT_IBI_SIR_Raise(struct mec_i3c_ctx *ctx,
313 int MEC_HAL_I3C_TGT_IBI_MR_Raise(struct mec_i3c_ctx *ctx);
315 void MEC_HAL_I3C_Target_Interrupts_Init(struct mec_i3c_ctx *ctx);
317 void MEC_HAL_I3C_TGT_IBI_SIR_Residual_handle(struct mec_i3c_ctx *ctx);
319 void MEC_HAL_I3C_TGT_Error_Recovery(struct mec_i3c_ctx *ctx, uint8_t err_sts);
322 void MEC_HAL_I3C_DO_TGT_Xfer(struct mec_i3c_ctx *ctx,  uint8_t *data_buf, uint16_t data_len,
325 void MEC_HAL_I3C_DO_TGT_Xfer(struct mec_i3c_ctx *ctx, uint8_t *data_buf, uint16_t data_len);
328 void MEC_HAL_I3C_Target_MRL_MWL_update(struct mec_i3c_ctx *ctx, uint16_t *max_rd_len,
331 void MEC_HAL_I3C_Target_MRL_MWL_set(struct mec_i3c_ctx *ctx, uint16_t max_rd_len,
334 void MEC_HAL_I3C_SDCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t idx,
337 void MEC_HAL_I3C_TGT_DEFTGTS_DAT_write(struct mec_i3c_ctx *ctx, uint16_t DCT_start,
340 void MEC_HAL_I3C_TGT_RoleSwitch_Resume(struct mec_i3c_ctx *ctx);
342 void MEC_HAL_I3C_GIRQ_Status_Clr(struct mec_i3c_ctx *ctx);
344 void MEC_HAL_I3C_GIRQ_CTRL(struct mec_i3c_ctx *ctx, int flags);
346 int MEC_HAL_I3C_GIRQ_Status(struct mec_i3c_ctx *ctx);
348 int MEC_HAL_I3C_GIRQ_Result(struct mec_i3c_ctx *ctx);