370 int mec_hal_espi_taf_pr_set(struct mec_espi_taf_regs *regs, struct espi_taf_pr *pr)  in mec_hal_espi_taf_pr_set()  argument
372     if (!taf_regs_valid(regs) || !pr || (pr->pr_num >= MEC_ESPI_TAF_PROT_REG_MAX)) {  in mec_hal_espi_taf_pr_set()
376     if (!MEC_IS_PTR_ALIGNED4K(pr->start) || !MEC_IS_PTR_ALIGNED4K(pr->size)) {  in mec_hal_espi_taf_pr_set()
380     volatile struct mec_espi_taf_pr_regs *pregs = &regs->PR[pr->pr_num];  in mec_hal_espi_taf_pr_set()
382     if (pr->flags & MEC_BIT(MCHP_TAF_PR_FLAG_ENABLE)) {  in mec_hal_espi_taf_pr_set()
383         pregs->START =  (pr->start >> MEC_TAF_PR_UNIT_SHIFT) & MEC_TAF_PR_START_LIM_MASK;  in mec_hal_espi_taf_pr_set()
384         pregs->LIMIT = (((pr->start + pr->size - 1u) >> MEC_TAF_PR_UNIT_SHIFT)  in mec_hal_espi_taf_pr_set()
386         pregs->WRBM = pr->req_bm_we;  in mec_hal_espi_taf_pr_set()
387         pregs->RDBM = pr->req_bm_rd;  in mec_hal_espi_taf_pr_set()
389         regs->PR_DIRTY = MEC_BIT(pr->pr_num);  in mec_hal_espi_taf_pr_set()
391         if (pr->flags & MEC_BIT(MCHP_TAF_PR_FLAG_LOCK)) {  in mec_hal_espi_taf_pr_set()
392             regs->PR_LOCK |= MEC_BIT(pr->pr_num);  in mec_hal_espi_taf_pr_set()
399         regs->PR_DIRTY = MEC_BIT(pr->pr_num);  in mec_hal_espi_taf_pr_set()