Lines Matching refs:MEC5_DMAC_NUM_CHANNELS
46 #if MEC5_DMAC_NUM_CHANNELS == 20
56 const uint32_t dmac_ecia_info_table[MEC5_DMAC_NUM_CHANNELS] = {
65 #if MEC5_DMAC_NUM_CHANNELS == 20
83 struct mec_dma_chan_regs_save dbg_mec_dma[MEC5_DMAC_NUM_CHANNELS];
88 if (channel < MEC5_DMAC_NUM_CHANNELS) { in dmac_get_ecia_info()
118 for (uint8_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in dma_clr_ia_all()
168 if (channel >= MEC5_DMAC_NUM_CHANNELS) { in mec_hal_dma_chan_ia_status_clr()
191 if (channel >= MEC5_DMAC_NUM_CHANNELS) { in mec_hal_dma_chan_ia_enable()
202 if (channel >= MEC5_DMAC_NUM_CHANNELS) { in mec_hal_dma_chan_ia_disable()
217 for (uint32_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in mec_hal_dma_chan_ia_enable_mask()
232 for (uint32_t chan = 0; chan < MEC5_DMAC_NUM_CHANNELS; chan++) { in mec_hal_dma_chan_ia_disable_mask()