Lines Matching refs:CONFIG
85 return (uint8_t)((regs->CONFIG & MEC_BBLED_CONFIG_PWM_SZ_Msk) >> MEC_BBLED_CONFIG_PWM_SZ_Pos); in bbled_get_pwm_size()
90 regs->CONFIG = (regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_PWM_SZ_Msk) | in bbled_set_pwm_size()
97 regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos); in bbled_set_clk_src()
99 regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos); in bbled_set_clk_src()
107 regs->CONFIG = ((regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_WDTRLD_Msk) | in bbled_set_wdt_reload()
113 regs->CONFIG = ((regs->CONFIG & (uint32_t)~MEC_BBLED_CONFIG_CTRL_Msk) | in bbled_set_mode()
119 return (uint8_t)((regs->CONFIG & MEC_BBLED_CONFIG_CTRL_Msk) >> MEC_BBLED_CONFIG_CTRL_Pos); in bbled_get_mode()
136 regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_SYNC_Pos); in mec_hal_bbled_synchronize_enable()
138 regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_SYNC_Pos); in mec_hal_bbled_synchronize_enable()
144 if (regs->CONFIG & MEC_BBLED_CONFIG_CTRL_Msk) { in mec_hal_bbled_is_off()
154 regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_ASYM_Pos); in mec_hal_bbled_asym_enable()
156 regs->CONFIG &= (uint32_t)~MEC_BIT(MEC_BBLED_CONFIG_ASYM_Pos); in mec_hal_bbled_asym_enable()
174 regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_SRST_Pos); in mec_hal_bbled_init()
176 regs->CONFIG &= (uint32_t)~MEC_BBLED_CONFIG_CTRL_Msk; in mec_hal_bbled_init()
177 regs->CONFIG |= (MEC_BBLED_CONFIG_CTRL_OFF << MEC_BBLED_CONFIG_CTRL_Pos); in mec_hal_bbled_init()
223 regs->CONFIG |= MEC_BIT(MEC_BBLED_CONFIG_UPDATE_Pos); in mec_hal_bbled_enable_update()
228 if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_UPDATE_Pos)) { in mec_hal_bbled_enable_is_update()
237 if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos)) { in mec_hal_bbled_clk_freq()
287 if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos)) { in mec_hal_bbled_blink_clk_sel_get()
414 if (regs->CONFIG & MEC_BIT(MEC_BBLED_CONFIG_CLKSRC_Pos)) { in mec_hal_bbled_blink_config_get()