67 #define MCHP_NVIC_SET_EN(n) \  argument
68 	REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) * 4u))
70 #define MCHP_NVIC_CLR_EN(n) \  argument
71 	REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) * 4u))
73 #define MCHP_NVIC_SET_PEND(n) \  argument
74 	REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) * 4u))
76 #define MCHP_NVIC_CLR_PEND(n) \  argument
77 	REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) * 4u))
144 #define MCHP_GIRQ_TO_AGGR_NVIC(n) (((n) < 23) ? ((n)-8) : ((n)-9))  argument
147 #define MCHP_GIRQ_SRC_ADDR(n) \  argument
148 	((MCHP_ECIA_ADDR + 0x00u) + (((uint32_t)(n) - 8u) * 0x14u))
150 #define MCHP_GIRQ_ENSET_ADDR(n) \  argument
151 	((MCHP_ECIA_ADDR + 0x04u) + (((uint32_t)(n) - 8u) * 0x14u))
153 #define MCHP_GIRQ_RESULT_ADDR(n) \  argument
154 	((MCHP_ECIA_ADDR + 0x08u) + (((uint32_t)(n) - 8u) * 0x14u))
156 #define MCHP_GIRQ_ENCLR_ADDR(n) \  argument
157 	((MCHP_ECIA_ADDR + 0x0cu) + (((uint32_t)(n) - 8u) * 0x14u))
271 #define MCHP_GIRQ_BLK_SETEN(n) \  argument
272 	REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = BIT(n)
274 #define MCHP_GIRQ_BLK_CLREN(n) \  argument
275 	REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = BIT(n)
277 #define MCHP_GIRQ_BLK_IS_ACTIVE(n) \  argument
278 	((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & BIT(n)) != 0u)
281 #define MCHP_GIRQ_SRC(n) REG32(MCHP_GIRQ_SRC_ADDR(n))  argument
283 #define MCHP_GIRQ_ENSET(n) REG32(MCHP_GIRQ_ENSET_ADDR(n))  argument
285 #define MCHP_GIRQ_RESULT(n) REG32(MCHP_GIRQ_RESULT_ADDR(n))  argument
286 #define MCHP_GIRQ_ENCLR(n)  REG32(MCHP_GIRQ_ENCLR_ADDR(n))  argument
292 #define MCHP_GIRQ_SRC_CLR(n, pos) \  argument
293 	REG32(MCHP_GIRQ_SRC_ADDR(n)) = BIT(pos)
295 #define MCHP_GIRQ_SET_EN(n, pos) \  argument
296 	REG32(MCHP_GIRQ_ENSET_ADDR(n)) = BIT(pos)
298 #define MCHP_GIRQ_CLR_EN(n, pos) \  argument
299 	REG32(MCHP_GIRQ_ENCLR_ADDR(n)) = BIT(pos)
301 #define MCHP_GIRQ_IS_RESULT(n, pos) \  argument
302 	((REG32(MCHP_GIRQ_RESULT_ADDR(n)) & BIT(pos)) != 0u)