89  * This structure is only intended to be used by the sedi_uart_save_context and
113 	bool context_valid; /**< Indicates whether saved context is valid. */
266 	/* Wait till reset bit is cleared */  in uart_soft_rst_instance()
438 				 * register still is transmitting the last 8  in sedi_uart_isr_handler()
441 				 * is still  in sedi_uart_isr_handler()
443 				 * is  in sedi_uart_isr_handler()
458 			 * If we are starting the transfer then the TX FIFO is  in sedi_uart_isr_handler()
474 			 * TX buffer is empty.  in sedi_uart_isr_handler()
500 				 * NOTE: Returned len is 0 for now, this might  in sedi_uart_isr_handler()
574 			/* Remove the address from FIFO as address match is  in sedi_uart_isr_handler()
1022 	 * generated as rx line held low when rs485 is not enabled.  in sedi_uart_rs485_enable()
1287 		/* When DLAB is set, DLL and DLH registers can be accessed. */  in sedi_uart_restore_context()
1313 		 * default config is applied for this register.  in sedi_uart_restore_context()
1326 	/* As fifos are enabled and ptime is enabled the thre bit  in is_tx_fifo_full()
1586 	/* Report error if there is an ongoing async read. */  in sedi_uart_enable_unsol_rx()
1645 	/* read_idx is the last read location so adding 1 for next valid  in sedi_uart_get_unsol_data()
1646 	 * location, similarly write_idx is the last written location thus  in sedi_uart_get_unsol_data()