Lines Matching refs:ulConfig
126 uint32_t ulConfig; in Cy_EPHY_Reset() local
134 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Reset()
135 phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( ulConfig | PHYBMCR_RESET_Msk ) ); in Cy_EPHY_Reset()
139 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Reset()
140 if(_FLD2VAL(PHYBMCR_RESET, ulConfig) == 0UL) in Cy_EPHY_Reset()
148 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Reset()
149 phy->fnPhyWrite( phyAddress, PHYREG_00_BMCR, ( ulConfig & ( ~PHYBMCR_RESET_Msk ) ) ); in Cy_EPHY_Reset()
178 uint32_t ulConfig, reg, bmsr; in Cy_EPHY_Configure() local
186 phy->fnPhyRead( phyAddress, PHYREG_00_BMCR, &ulConfig ); in Cy_EPHY_Configure()
195 ulConfig |= PHYBMCR_AN_ENABLE_Msk; in Cy_EPHY_Configure()
197 ulConfig |= PHYBMCR_AN_RESTART_Msk; in Cy_EPHY_Configure()
211 …ulConfig &= ~( PHYBMCR_SPEED_1000_Msk | PHYBMCR_SPEED_100_Msk | PHYBMCR_FULL_DUPLEX_Msk | PHYBMCR_… in Cy_EPHY_Configure()
215 ulConfig |= PHYBMCR_SPEED_100_Msk; in Cy_EPHY_Configure()
219 ulConfig |= PHYBMCR_AN_ENABLE_Msk; in Cy_EPHY_Configure()
220 ulConfig |= PHYBMCR_SPEED_1000_Msk; in Cy_EPHY_Configure()
224 ulConfig &= ~PHYBMCR_SPEED_100_Msk; in Cy_EPHY_Configure()
234 ulConfig |= PHYBMCR_FULL_DUPLEX_Msk; in Cy_EPHY_Configure()
238 ulConfig &= ~PHYBMCR_FULL_DUPLEX_Msk; in Cy_EPHY_Configure()
250 phy->bmcr = ulConfig & ~PHYBMCR_ISOLATE_Msk; in Cy_EPHY_Configure()