Lines Matching refs:FLASHC

383 #define FLASHC_FLASH_CTL             (((FLASHC_Type *)(FLASHC))->FLASH_CTL)
384 #define FLASHC_FLASH_PWR_CTL         (((FLASHC_Type *)(FLASHC))->FLASH_PWR_CTL)
385 #define FLASHC_FLASH_CMD             (((FLASHC_Type *)(FLASHC))->FLASH_CMD)
386 #define FLASHC_ECC_CTL               (((FLASHC_Type *)(FLASHC))->ECC_CTL)
387 #define FLASHC_FM_SRAM_ECC_CTL0      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL0)
388 #define FLASHC_FM_SRAM_ECC_CTL1      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL1)
389 #define FLASHC_FM_SRAM_ECC_CTL2      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL2)
390 #define FLASHC_FM_SRAM_ECC_CTL3      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL3)
391 #define FLASHC_CM0_CA_CTL0           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL0)
392 #define FLASHC_CM0_CA_CTL1           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL1)
393 #define FLASHC_CM0_CA_CTL2           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL2)
394 #define FLASHC_CM0_CA_STATUS0        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS0)
395 #define FLASHC_CM0_CA_STATUS1        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS1)
396 #define FLASHC_CM0_CA_STATUS2        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS2)
397 #define FLASHC_CM0_STATUS            (((FLASHC_Type *)(FLASHC))->CM0_STATUS)
398 #define FLASHC_CM7_0_STATUS          (((FLASHC_Type *)(FLASHC))->CM7_0_STATUS)
399 #define FLASHC_CM7_1_STATUS          (((FLASHC_Type *)(FLASHC))->CM7_1_STATUS)
400 #define FLASHC_CRYPTO_BUFF_CTL       (((FLASHC_Type *)(FLASHC))->CRYPTO_BUFF_CTL)
401 #define FLASHC_DW0_BUFF_CTL          (((FLASHC_Type *)(FLASHC))->DW0_BUFF_CTL)
402 #define FLASHC_DW1_BUFF_CTL          (((FLASHC_Type *)(FLASHC))->DW1_BUFF_CTL)
403 #define FLASHC_DMAC_BUFF_CTL         (((FLASHC_Type *)(FLASHC))->DMAC_BUFF_CTL)
404 #define FLASHC_SLOW0_MS_BUFF_CTL     (((FLASHC_Type *)(FLASHC))->SLOW0_MS_BUFF_CTL)
405 #define FLASHC_SLOW1_MS_BUFF_CTL     (((FLASHC_Type *)(FLASHC))->SLOW1_MS_BUFF_CTL)