Lines Matching refs:obj
145 static inline void _cyhal_dma_dw_set_obj(cyhal_dma_t *obj) in _cyhal_dma_dw_set_obj() argument
147 …_cyhal_dma_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num… in _cyhal_dma_dw_set_obj()
151 static inline void _cyhal_dma_dw_free_obj(cyhal_dma_t *obj) in _cyhal_dma_dw_free_obj() argument
153 …_cyhal_dma_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num… in _cyhal_dma_dw_free_obj()
224 static inline _cyhal_system_irq_t _cyhal_dma_dw_get_irqn(cyhal_dma_t *obj) in _cyhal_dma_dw_get_irqn() argument
228 … if (obj->resource.block_num == 0 && obj->resource.channel_num < CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ) in _cyhal_dma_dw_get_irqn()
231 …return (_cyhal_system_irq_t)((uint8_t)m33syscpuss_interrupts_dw0_0_IRQn + obj->resource.channel_nu… in _cyhal_dma_dw_get_irqn()
233 … return (_cyhal_system_irq_t)((uint8_t)cpuss_interrupts_dw0_0_IRQn + obj->resource.channel_num); in _cyhal_dma_dw_get_irqn()
237 else if ((obj->resource.block_num == 0 && obj->resource.channel_num < CPUSS_DW0_CH_NR)) in _cyhal_dma_dw_get_irqn()
239 …(uint8_t)_CYHAL_DMA_GET_CPUSS_IRQN(0, CYHAL_DMA_DW0_MAX_CONTIGUOUS_IRQ) + (obj->resource.channel_n… in _cyhal_dma_dw_get_irqn()
244 … if (obj->resource.block_num == 1 && obj->resource.channel_num < CYHAL_DMA_DW1_MAX_CONTIGUOUS_IRQ) in _cyhal_dma_dw_get_irqn()
246 … return (_cyhal_system_irq_t)((uint16_t)cpuss_interrupts_dw1_0_IRQn + obj->resource.channel_num); in _cyhal_dma_dw_get_irqn()
249 else if (obj->resource.block_num == 1 && obj->resource.channel_num < CPUSS_DW1_CH_NR) in _cyhal_dma_dw_get_irqn()
251 …(uint8_t)_CYHAL_DMA_GET_CPUSS_IRQN(1, CYHAL_DMA_DW1_MAX_CONTIGUOUS_IRQ) + (obj->resource.channel_n… in _cyhal_dma_dw_get_irqn()
307 static inline cyhal_dma_event_t _cyhal_dma_dw_convert_interrupt_cause(cyhal_dma_t *obj, cy_en_dma_i… in _cyhal_dma_dw_convert_interrupt_cause() argument
327 if ((uint32_t)(hal_rslt & CYHAL_DMA_TRANSFER_COMPLETE) > 0 && obj->expected_bursts > 0) in _cyhal_dma_dw_convert_interrupt_cause()
329 obj->expected_bursts--; in _cyhal_dma_dw_convert_interrupt_cause()
330 if (0 == obj->expected_bursts) in _cyhal_dma_dw_convert_interrupt_cause()
333 obj->expected_bursts = (obj->descriptor_config.dw.interruptType == CY_DMA_X_LOOP) in _cyhal_dma_dw_convert_interrupt_cause()
334 ? obj->descriptor_config.dw.yCount in _cyhal_dma_dw_convert_interrupt_cause()
349 cyhal_dma_t *obj = _cyhal_dma_dw_get_obj(block, channel); in _cyhal_dma_dw_irq_handler() local
353 cyhal_dma_event_t event_type = _cyhal_dma_dw_convert_interrupt_cause(obj, cause); in _cyhal_dma_dw_irq_handler()
354 uint32_t events_to_callback = event_type & obj->irq_cause; in _cyhal_dma_dw_irq_handler()
355 if(obj->callback_data.callback != NULL && events_to_callback) in _cyhal_dma_dw_irq_handler()
357 …((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_… in _cyhal_dma_dw_irq_handler()
382 cy_rslt_t _cyhal_dma_dw_stage(cyhal_dma_t *obj) in _cyhal_dma_dw_stage() argument
384 if(CY_DMA_SUCCESS != Cy_DMA_Descriptor_Init(&obj->descriptor.dw, &obj->descriptor_config.dw)) in _cyhal_dma_dw_stage()
388 DW_Type* base = _cyhal_dma_dw_get_base(obj->resource.block_num); in _cyhal_dma_dw_stage()
389 …if(CY_DMA_SUCCESS != Cy_DMA_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dw)) in _cyhal_dma_dw_stage()
392 Cy_DMA_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMA_INTR_MASK); in _cyhal_dma_dw_stage()
398 uint32_t status = Cy_DMA_Channel_GetInterruptStatus(base, obj->resource.channel_num); in _cyhal_dma_dw_stage()
402 Cy_DMA_Channel_ClearInterrupt(base, obj->resource.channel_num); in _cyhal_dma_dw_stage()
407 _cyhal_system_irq_t irqn = _cyhal_dma_dw_get_irqn(obj); in _cyhal_dma_dw_stage()
408 uint32_t priority = (CYHAL_DMA_NO_INTR == obj->irq_cause) in _cyhal_dma_dw_stage()
417 SCB_CleanDCache_by_Addr((void *)&(obj->descriptor), sizeof(obj->descriptor)); in _cyhal_dma_dw_stage()
423 cy_rslt_t _cyhal_dma_dw_init(cyhal_dma_t *obj, cyhal_source_t *src, cyhal_dest_t *dest, uint8_t pri… in _cyhal_dma_dw_init() argument
429 CYHAL_RSC_DW, src, dest, _cyhal_dma_dw_get_src, _cyhal_dma_dw_get_dest, &obj->resource); in _cyhal_dma_dw_init()
434 obj->descriptor_config.dw = _cyhal_dma_dw_default_descriptor_config; in _cyhal_dma_dw_init()
435 obj->channel_config.dw = _cyhal_dma_dw_default_channel_config; in _cyhal_dma_dw_init()
436 obj->channel_config.dw.descriptor = &obj->descriptor.dw; in _cyhal_dma_dw_init()
437 obj->channel_config.dw.priority = priority; in _cyhal_dma_dw_init()
444 _cyhal_dma_dw_set_obj(obj); in _cyhal_dma_dw_init()
449 cy_rslt_t _cyhal_dma_dw_init_cfg(cyhal_dma_t *obj, const cyhal_dma_configurator_t *cfg) in _cyhal_dma_dw_init_cfg() argument
456 obj->resource = *(cfg->resource); in _cyhal_dma_dw_init_cfg()
457 obj->callback_data.callback = NULL; in _cyhal_dma_dw_init_cfg()
460 obj->descriptor_config.dw = *(cfg->dw_descriptor_config); in _cyhal_dma_dw_init_cfg()
461 obj->channel_config.dw = *(cfg->dw_channel_config); in _cyhal_dma_dw_init_cfg()
462 obj->channel_config.dw.descriptor = &obj->descriptor.dw; in _cyhal_dma_dw_init_cfg()
463 obj->expected_bursts = cfg->dw_descriptor_config->yCount; in _cyhal_dma_dw_init_cfg()
472 _cyhal_dma_dw_set_obj(obj); in _cyhal_dma_dw_init_cfg()
474 return _cyhal_dma_dw_stage(obj); in _cyhal_dma_dw_init_cfg()
477 void _cyhal_dma_dw_free(cyhal_dma_t *obj) in _cyhal_dma_dw_free() argument
479 Cy_DMA_Descriptor_DeInit(&obj->descriptor.dw); in _cyhal_dma_dw_free()
480 … Cy_DMA_Channel_DeInit(_cyhal_dma_dw_get_base(obj->resource.block_num), obj->resource.channel_num); in _cyhal_dma_dw_free()
482 _cyhal_irq_free(_cyhal_dma_dw_get_irqn(obj)); in _cyhal_dma_dw_free()
484 _cyhal_dma_dw_free_obj(obj); in _cyhal_dma_dw_free()
496 cy_rslt_t _cyhal_dma_dw_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) in _cyhal_dma_dw_configure() argument
499 if(_cyhal_dma_dw_is_busy(obj)) in _cyhal_dma_dw_configure()
508 obj->descriptor_config.dw.srcAddress = (void*)cfg->src_addr; in _cyhal_dma_dw_configure()
509 obj->descriptor_config.dw.dstAddress = (void*)cfg->dst_addr; in _cyhal_dma_dw_configure()
510 obj->descriptor_config.dw.nextDescriptor = &obj->descriptor.dw; in _cyhal_dma_dw_configure()
513 obj->descriptor_config.dw.channelState = CY_DMA_CHANNEL_ENABLED; in _cyhal_dma_dw_configure()
517 obj->descriptor_config.dw.channelState = CY_DMA_CHANNEL_DISABLED; in _cyhal_dma_dw_configure()
521 obj->descriptor_config.dw.dataSize = CY_DMA_BYTE; in _cyhal_dma_dw_configure()
523 obj->descriptor_config.dw.dataSize = CY_DMA_HALFWORD; in _cyhal_dma_dw_configure()
525 obj->descriptor_config.dw.dataSize = CY_DMA_WORD; in _cyhal_dma_dw_configure()
531 obj->descriptor_config.dw.srcTransferSize = in _cyhal_dma_dw_configure()
532 obj->descriptor_config.dw.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA; in _cyhal_dma_dw_configure()
533 if (obj->direction == CYHAL_DMA_DIRECTION_PERIPH2MEM) in _cyhal_dma_dw_configure()
534 obj->descriptor_config.dw.srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD; in _cyhal_dma_dw_configure()
535 else if (obj->direction == CYHAL_DMA_DIRECTION_MEM2PERIPH) in _cyhal_dma_dw_configure()
536 obj->descriptor_config.dw.dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD; in _cyhal_dma_dw_configure()
543 obj->descriptor_config.dw.srcXincrement = cfg->src_increment; in _cyhal_dma_dw_configure()
544 obj->descriptor_config.dw.dstXincrement = cfg->dst_increment; in _cyhal_dma_dw_configure()
548 obj->descriptor_config.dw.descriptorType = CY_DMA_2D_TRANSFER; in _cyhal_dma_dw_configure()
549 obj->descriptor_config.dw.xCount = cfg->burst_size; in _cyhal_dma_dw_configure()
550 obj->descriptor_config.dw.yCount = cfg->length / cfg->burst_size; in _cyhal_dma_dw_configure()
551 obj->descriptor_config.dw.srcYincrement = cfg->src_increment * (int32_t)cfg->burst_size; in _cyhal_dma_dw_configure()
552 obj->descriptor_config.dw.dstYincrement = cfg->dst_increment * (int32_t)cfg->burst_size; in _cyhal_dma_dw_configure()
556 obj->descriptor_config.dw.descriptorType = CY_DMA_1D_TRANSFER; in _cyhal_dma_dw_configure()
557 obj->descriptor_config.dw.xCount = cfg->length; in _cyhal_dma_dw_configure()
558 obj->descriptor_config.dw.yCount = 1; in _cyhal_dma_dw_configure()
559 obj->descriptor_config.dw.srcYincrement = 0; in _cyhal_dma_dw_configure()
560 obj->descriptor_config.dw.dstYincrement = 0; in _cyhal_dma_dw_configure()
567 obj->expected_bursts = obj->descriptor_config.dw.yCount; in _cyhal_dma_dw_configure()
568 obj->descriptor_config.dw.interruptType = CY_DMA_X_LOOP; in _cyhal_dma_dw_configure()
569 if (obj->source == CYHAL_TRIGGER_CPUSS_ZERO) // If not overridden by connect_digital() in _cyhal_dma_dw_configure()
570 obj->descriptor_config.dw.triggerInType = CY_DMA_X_LOOP; in _cyhal_dma_dw_configure()
574 obj->expected_bursts = 1; in _cyhal_dma_dw_configure()
575 obj->descriptor_config.dw.interruptType = CY_DMA_DESCR; in _cyhal_dma_dw_configure()
576 if (obj->source == CYHAL_TRIGGER_CPUSS_ZERO) // If not overridden by connect_digital() in _cyhal_dma_dw_configure()
577 obj->descriptor_config.dw.triggerInType = CY_DMA_DESCR; in _cyhal_dma_dw_configure()
580 return _cyhal_dma_dw_stage(obj); in _cyhal_dma_dw_configure()
583 cy_rslt_t _cyhal_dma_dw_enable(cyhal_dma_t *obj) in _cyhal_dma_dw_enable() argument
585 DW_Type* base = _cyhal_dma_dw_get_base(obj->resource.block_num); in _cyhal_dma_dw_enable()
586 Cy_DMA_Channel_Enable(base, obj->resource.channel_num); in _cyhal_dma_dw_enable()
590 cy_rslt_t _cyhal_dma_dw_disable(cyhal_dma_t *obj) in _cyhal_dma_dw_disable() argument
592 DW_Type* base = _cyhal_dma_dw_get_base(obj->resource.block_num); in _cyhal_dma_dw_disable()
593 Cy_DMA_Channel_Disable(base, obj->resource.channel_num); in _cyhal_dma_dw_disable()
597 cy_rslt_t _cyhal_dma_dw_start_transfer(cyhal_dma_t *obj) in _cyhal_dma_dw_start_transfer() argument
600 if(_cyhal_dma_dw_is_busy(obj)) in _cyhal_dma_dw_start_transfer()
606 …uint32_t trigline = _cyhal_dma_dw_get_trigger_line(obj->resource.block_num, obj->resource.channel_… in _cyhal_dma_dw_start_transfer()
617 void _cyhal_dma_dw_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, b… in _cyhal_dma_dw_enable_event() argument
620 obj->irq_cause |= event; in _cyhal_dma_dw_enable_event()
622 obj->irq_cause &= ~event; in _cyhal_dma_dw_enable_event()
624 _cyhal_irq_set_priority(_cyhal_dma_dw_get_irqn(obj), intr_priority); in _cyhal_dma_dw_enable_event()
627 bool _cyhal_dma_dw_is_busy(cyhal_dma_t *obj) in _cyhal_dma_dw_is_busy() argument
633 …return _cyhal_dma_dw_get_base(obj->resource.block_num)->PENDING & (1 << obj->resource.channel_num); in _cyhal_dma_dw_is_busy()
637 …return DW_CH_STATUS(_cyhal_dma_dw_get_base(obj->resource.block_num), obj->resource.channel_num) & … in _cyhal_dma_dw_is_busy()
639 …return DW_CH_STATUS(_cyhal_dma_dw_get_base(obj->resource.block_num), obj->resource.channel_num) & … in _cyhal_dma_dw_is_busy()
681 cy_rslt_t _cyhal_dma_dw_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t … in _cyhal_dma_dw_connect_digital() argument
688 CY_ASSERT(obj->source == CYHAL_TRIGGER_CPUSS_ZERO); in _cyhal_dma_dw_connect_digital()
690 obj->descriptor_config.dw.triggerInType = _cyhal_convert_input_t(input); in _cyhal_dma_dw_connect_digital()
691 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_IN_TYPE_Msk; in _cyhal_dma_dw_connect_digital()
692 …obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, obj->descriptor_config.dw.triggerInType); in _cyhal_dma_dw_connect_digital()
694 SCB_CleanDCache_by_Addr((void *)&(obj->descriptor), sizeof(obj->descriptor)); in _cyhal_dma_dw_connect_digital()
697 cyhal_dest_t dest = _cyhal_dma_dw_get_dest(obj->resource.block_num, obj->resource.channel_num); in _cyhal_dma_dw_connect_digital()
702 obj->source = source; in _cyhal_dma_dw_connect_digital()
708 cy_rslt_t _cyhal_dma_dw_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *… in _cyhal_dma_dw_enable_output() argument
715 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_OUT_TYPE_Msk; in _cyhal_dma_dw_enable_output()
716 obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, _cyhal_convert_output_t(output)); in _cyhal_dma_dw_enable_output()
718 SCB_CleanDCache_by_Addr((void *)&(obj->descriptor), sizeof(obj->descriptor)); in _cyhal_dma_dw_enable_output()
721 *source = _cyhal_dma_dw_get_src(obj->resource.block_num, obj->resource.channel_num); in _cyhal_dma_dw_enable_output()
726 cy_rslt_t _cyhal_dma_dw_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input… in _cyhal_dma_dw_disconnect_digital() argument
732 CY_ASSERT(obj->source != CYHAL_TRIGGER_CPUSS_ZERO); in _cyhal_dma_dw_disconnect_digital()
737 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_IN_TYPE_Msk; in _cyhal_dma_dw_disconnect_digital()
738 …obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, _cyhal_dma_dw_default_descriptor_config.… in _cyhal_dma_dw_disconnect_digital()
740 SCB_CleanDCache_by_Addr((void *)&(obj->descriptor), sizeof(obj->descriptor)); in _cyhal_dma_dw_disconnect_digital()
743 cyhal_dest_t dest = _cyhal_dma_dw_get_dest(obj->resource.block_num, obj->resource.channel_num); in _cyhal_dma_dw_disconnect_digital()
748 obj->source = CYHAL_TRIGGER_CPUSS_ZERO; in _cyhal_dma_dw_disconnect_digital()
754 cy_rslt_t _cyhal_dma_dw_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output) in _cyhal_dma_dw_disable_output() argument
762 obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_OUT_TYPE_Msk; in _cyhal_dma_dw_disable_output()
763 …obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, _cyhal_dma_dw_default_descriptor_config… in _cyhal_dma_dw_disable_output()
765 SCB_CleanDCache_by_Addr((void *)&(obj->descriptor), sizeof(obj->descriptor)); in _cyhal_dma_dw_disable_output()