Lines Matching refs:src_freq
1489 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(0); in _cyhal_clock_set_enabled_fll() local
1490 …uint32_t fll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.… in _cyhal_clock_set_enabled_fll()
1494 old_freq = src_freq >> div; in _cyhal_clock_set_enabled_fll()
1498 new_freq = src_freq >> div; in _cyhal_clock_set_enabled_fll()
1533 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(0); in _cyhal_clock_set_frequency_fll() local
1535 if (0 == src_freq) in _cyhal_clock_set_frequency_fll()
1539 …uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * (uint64_t)cfg.fllMult, (uint32_t)cfg.… in _cyhal_clock_set_frequency_fll()
1553 rslt = Cy_SysClk_FllConfigure(src_freq, hz/*new_freq*/, CY_SYSCLK_FLLPLL_OUTPUT_AUTO); in _cyhal_clock_set_frequency_fll()
1652 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(pll_idx); in _cyhal_clock_set_enabled_pll() local
1659 …uint32_t pll_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * feedbackDiv, referenceDiv * outputDiv… in _cyhal_clock_set_enabled_pll()
1664 old_freq = src_freq >> div; in _cyhal_clock_set_enabled_pll()
1668 new_freq = src_freq >> div; in _cyhal_clock_set_enabled_pll()
1731 uint32_t src_freq = Cy_SysClk_ClkPathMuxGetFrequency(pll_idx); in _cyhal_clock_set_frequency_pll() local
1738 …uint32_t old_freq = CY_SYSLIB_DIV_ROUND((uint64_t)src_freq * feedbackDiv, referenceDiv * outputDiv… in _cyhal_clock_set_frequency_pll()