Lines Matching refs:sysClkDiv
56 … cy_en_ble_eco_sys_clk_div_t sysClkDiv);
234 …_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_eco_sys_clk_div_t sysClkDiv, in Cy_BLE_EcoConfigure() argument
242 ecoConfigParams.sysClkDiv = sysClkDiv; in Cy_BLE_EcoConfigure()
253 if( (freq > CY_BLE_BLESS_ECO_FREQ_32MHZ) || (sysClkDiv > CY_BLE_SYS_ECO_CLK_DIV_8) || in Cy_BLE_EcoConfigure()
416 status = Cy_BLE_HAL_MxdRadioEnableClocks(freq, sysClkDiv); in Cy_BLE_EcoConfigure()
735 cy_en_ble_eco_sys_clk_div_t sysClkDiv) in Cy_BLE_HAL_MxdRadioEnableClocks() argument
811 if(sysClkDiv >= CY_BLE_SYS_ECO_CLK_DIV_4) in Cy_BLE_HAL_MxdRadioEnableClocks()
817 blerdDivider = (uint16_t)sysClkDiv; in Cy_BLE_HAL_MxdRadioEnableClocks()
824 cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv); in Cy_BLE_HAL_MxdRadioEnableClocks()
828 if(sysClkDiv >= CY_BLE_SYS_ECO_CLK_DIV_2) in Cy_BLE_HAL_MxdRadioEnableClocks()
834 blerdDivider = (uint16_t)sysClkDiv; in Cy_BLE_HAL_MxdRadioEnableClocks()
841 cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv); in Cy_BLE_HAL_MxdRadioEnableClocks()
850 ecoSysDivider = (uint16_t)sysClkDiv - blerdDivider; in Cy_BLE_HAL_MxdRadioEnableClocks()