Lines Matching +full:license +full:- +full:path
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
11 * SPDX-License-Identifier: Apache-2.0
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
17 * http://www.apache.org/licenses/LICENSE-2.0
20 * distributed under the License is distributed on an "AS IS" BASIS,
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
35 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 17.2', 24, \
37 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.6', 6, \
83 { /* 16-bit divider */ in Cy_SysClk_PeriphGetDivider()
138 { /* 24.5-bit divider */ in Cy_SysClk_PeriphGetFracDivider()
233 /* First, disable the divider that is to be phase-aligned. in Cy_SysClk_PeriphEnablePhaseAlignDivider()
291 uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider(); /* peri prescaler (1-256) */ in Cy_SysClk_ClkSlowGetFrequency()
293 /* Divide the path input frequency down and return the result */ in Cy_SysClk_ClkSlowGetFrequency()
552 uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider(); /* peri prescaler (1-256) */ in Cy_SysClk_ClkPeriGetFrequency()
554 /* Divide the path input frequency down and return the result */ in Cy_SysClk_ClkPeriGetFrequency()
590 uint32_t locDiv = 1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider(); /* fast prescaler (1-256) */ in Cy_SysClk_ClkFastGetFrequency()
592 /* Divide the path input frequency down and return the result */ in Cy_SysClk_ClkFastGetFrequency()
796 … CY_PRA_REG32_CLR_SET(CY_PRA_INDX_SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); in Cy_SysClk_ClkMfSetDivider()
798 CY_REG32_CLR_SET(SRSS_CLK_MF_SELECT, SRSS_CLK_MF_SELECT_MFCLK_DIV, divider - 1UL); in Cy_SysClk_ClkMfSetDivider()
814 uint32_t locDiv = Cy_SysClk_ClkMfGetDivider(); /* clkMf prescaler (1-256) */ in Cy_SysClk_ClkMfGetFrequency()
816 /* Divide the path input frequency down and return the result */ in Cy_SysClk_ClkMfGetFrequency()
834 for (; (Cy_SysClk_WcoOkay() == false) && (0UL != timeoutus); timeoutus--) in Cy_SysClk_WcoEnable()
1099 * The input is 32-bit wide.
1100 * The result is 16-bit wide.
1206 … /* 10^9 / (5 * 4 * 4 * PI^2) = 1266514,7955292221430484932901216.. -> 126651, scaled by 10 */ in Cy_SysClk_EcoConfigure()
1258 … for (; (CY_SYSCLK_ECOSTAT_STABLE != Cy_SysClk_EcoGetStatus()) && (0UL != timeoutus); timeoutus--) in Cy_SysClk_EcoEnable()
1340 uint32_t freq = 0UL; /* The path mux output frequency in Hz, 0 = an unknown frequency */ in Cy_SysClk_ClkPathMuxGetFrequency()
1342 /* Get the frequency of the source, i.e., the path mux input */ in Cy_SysClk_ClkPathMuxGetFrequency()
1392 if (clkPath == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ in Cy_SysClk_ClkPathGetFrequency()
1396 else if (clkPath <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ in Cy_SysClk_ClkPathGetFrequency()
1402 /* Do nothing with the path mux frequency */ in Cy_SysClk_ClkPathGetFrequency()
1507 …ormula is lock tolerance = 1.5 * fllMult * (((1 + CCO accuracy) / (1 - source clock accuracy)) - 1) in Cy_SysClk_FllConfigure()
1528 for(config.igain = CY_SYSCLK_FLL_GAIN_IDX; config.igain != 0UL; config.igain--) in Cy_SysClk_FllConfigure()
1539 config.igain--; in Cy_SysClk_FllConfigure()
1543 … /* then find the largest PGAIN value that is less than or equal to ki_p - igain */ in Cy_SysClk_FllConfigure()
1544 for(config.pgain = CY_SYSCLK_FLL_GAIN_IDX; config.pgain != 0UL; config.pgain--) in Cy_SysClk_FllConfigure()
1546 if(locpgain <= (ki_p - locigain)) in Cy_SysClk_FllConfigure()
1556 config.pgain--; in Cy_SysClk_FllConfigure()
1616 …CY_ASSERT_L1(config->fllMult <= (SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk >> SRSS_CLK_FLL_CONFIG_FLL_MULT_… in Cy_SysClk_FllManualConfigure()
1618 SRSS_CLK_FLL_CONFIG = _VAL2FLD(SRSS_CLK_FLL_CONFIG_FLL_MULT, config->fllMult) | in Cy_SysClk_FllManualConfigure()
1619 _BOOL2FLD(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, config->enableOutputDiv); in Cy_SysClk_FllManualConfigure()
1623 …CY_ASSERT_L1(config->refDiv <= (SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk >> SRSS_CLK_FLL_CONFIG2_FLL_R… in Cy_SysClk_FllManualConfigure()
1624 …CY_ASSERT_L1(config->lockTolerance <= (SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk >> SRSS_CLK_FLL_CONFIG2_L… in Cy_SysClk_FllManualConfigure()
1626 SRSS_CLK_FLL_CONFIG2 = _VAL2FLD(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, config->refDiv) | in Cy_SysClk_FllManualConfigure()
1627 _VAL2FLD(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, config->lockTolerance); in Cy_SysClk_FllManualConfigure()
1631 …CY_ASSERT_L1(config->igain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_L… in Cy_SysClk_FllManualConfigure()
1632 …CY_ASSERT_L1(config->pgain <= (SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk >> SRSS_CLK_FLL_CONFIG3_FLL_L… in Cy_SysClk_FllManualConfigure()
1633 …CY_ASSERT_L1(config->settlingCount <= (SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk >> SRSS_CLK_FLL_CON… in Cy_SysClk_FllManualConfigure()
1635 SRSS_CLK_FLL_CONFIG3 = _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, config->igain) | in Cy_SysClk_FllManualConfigure()
1636 _VAL2FLD(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, config->pgain) | in Cy_SysClk_FllManualConfigure()
1637 … _VAL2FLD(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, config->settlingCount) | in Cy_SysClk_FllManualConfigure()
1638 _VAL2FLD(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, config->outputMode); in Cy_SysClk_FllManualConfigure()
1642 CY_ASSERT_L1(CY_SYSCLK_FLL_IS_CCO_RANGE_VALID(config->ccoRange)); in Cy_SysClk_FllManualConfigure()
1643 …CY_ASSERT_L1(config->cco_Freq <= (SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk >> SRSS_CLK_FLL_CONFIG4_CCO_FR… in Cy_SysClk_FllManualConfigure()
1645 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_RANGE, (uint32_t)(config->ccoRange… in Cy_SysClk_FllManualConfigure()
1646 …CY_REG32_CLR_SET(SRSS_CLK_FLL_CONFIG4, SRSS_CLK_FLL_CONFIG4_CCO_FREQ, (uint32_t)(config->cco_Freq)… in Cy_SysClk_FllManualConfigure()
1661 config->fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, tempReg); in Cy_SysClk_FllGetConfiguration()
1662 config->enableOutputDiv = _FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, tempReg); in Cy_SysClk_FllGetConfiguration()
1665 config->refDiv = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, tempReg); in Cy_SysClk_FllGetConfiguration()
1666 config->lockTolerance = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG2_LOCK_TOL, tempReg); in Cy_SysClk_FllGetConfiguration()
1669 config->igain = (uint8_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN, tempReg); in Cy_SysClk_FllGetConfiguration()
1670 config->pgain = (uint8_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN, tempReg); in Cy_SysClk_FllGetConfiguration()
1671 config->settlingCount = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT, tempReg); in Cy_SysClk_FllGetConfiguration()
1672 …config->outputMode = (cy_en_fll_pll_output_mode_t)((uint32_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG3_BY… in Cy_SysClk_FllGetConfiguration()
1675 …config->ccoRange = (cy_en_fll_cco_ranges_t)((uint32_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_RAN… in Cy_SysClk_FllGetConfiguration()
1676 config->cco_Freq = (uint16_t)_FLD2VAL(SRSS_CLK_FLL_CONFIG4_CCO_FREQ, tempReg); in Cy_SysClk_FllGetConfiguration()
1695 timeoutus--) in Cy_SysClk_FllEnable()
1712 timeoutus--) in Cy_SysClk_FllEnable()
1753 #define CY_SYSCLK_PLL_MIN_FB_DIV ((config->lfMode) ? CY_SYSCLK_PLL_MIN_FB_DIV_LF : CY_SYSCLK_…
1754 #define CY_SYSCLK_PLL_MAX_FB_DIV ((config->lfMode) ? CY_SYSCLK_PLL_MAX_FB_DIV_LF : CY_SYSCLK_…
1762 #define CY_SYSCLK_PLL_MIN_FVCO ((config->lfMode) ? CY_SYSCLK_PLL_MIN_FVCO_LF : CY_SYSCLK_PL…
1763 #define CY_SYSCLK_PLL_MAX_FVCO ((config->lfMode) ? CY_SYSCLK_PLL_MAX_FVCO_LF : CY_SYSCLK_PL…
1774 clkPath--; /* to correctly access PLL config and status registers structures */ in Cy_SysClk_PllIsEnabled()
1782 clkPath--; /* to correctly access PLL config and status registers structures */ in Cy_SysClk_PllLocked()
1795 clkPath--; /* to correctly access PLL config and status registers structures */ in Cy_SysClk_PllLostLock()
1808 clkPath--; /* to correctly access PLL config and status registers structures */ in Cy_SysClk_PllDisable()
1832 …if (((config->inputFreq) < CY_SYSCLK_PLL_MIN_IN_FREQ) || (CY_SYSCLK_PLL_MAX_IN_FREQ < (config->… in Cy_SysClk_PllConfigure()
1833 …((config->outputFreq) < CY_SYSCLK_PLL_MIN_OUT_FREQ) || (CY_SYSCLK_PLL_MAX_OUT_FREQ < (config->outp… in Cy_SysClk_PllConfigure()
1843 if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_PllConfigure()
1858 … uint32_t fvco = (uint32_t)(((uint64_t)(config->inputFreq) * (uint64_t)p) / (uint64_t)q); in Cy_SysClk_PllConfigure()
1866 uint32_t fout = ((p * config->inputFreq) / q) / out; in Cy_SysClk_PllConfigure()
1867 if ((uint32_t)abs((int32_t)fout - (int32_t)(config->outputFreq)) < in Cy_SysClk_PllConfigure()
1868 (uint32_t)abs((int32_t)foutBest - (int32_t)(config->outputFreq))) in Cy_SysClk_PllConfigure()
1870 if (foutBest == (config->outputFreq)) in Cy_SysClk_PllConfigure()
1886 manualConfig.lfMode = config->lfMode; in Cy_SysClk_PllConfigure()
1897 manualConfig.outputMode = config->outputMode; in Cy_SysClk_PllConfigure()
1911 if (clkPath > CY_SRSS_NUM_PLL) /* invalid clock path number */ in Cy_SysClk_PllManualConfigure()
1920 …else if ((config->outputDiv < CY_SYSCLK_PLL_MIN_OUTPUT_DIV) || (CY_SYSCLK_PLL_MAX_OUTPUT_DIV < … in Cy_SysClk_PllManualConfigure()
1921 …(config->referenceDiv < CY_SYSCLK_PLL_MIN_REF_DIV) || (CY_SYSCLK_PLL_MAX_REF_DIV < config->r… in Cy_SysClk_PllManualConfigure()
1922 …(config->feedbackDiv < CY_SYSCLK_PLL_MIN_FB_DIV) || (CY_SYSCLK_PLL_MAX_FB_DIV < config->f… in Cy_SysClk_PllManualConfigure()
1935 clkPath--; /* to correctly access PLL config registers structure */ in Cy_SysClk_PllManualConfigure()
1938 if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_PllManualConfigure()
1941 _VAL2FLD(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, config->feedbackDiv) | in Cy_SysClk_PllManualConfigure()
1942 _VAL2FLD(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, config->referenceDiv) | in Cy_SysClk_PllManualConfigure()
1943 _VAL2FLD(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, config->outputDiv) | in Cy_SysClk_PllManualConfigure()
1944 _VAL2FLD(SRSS_CLK_PLL_CONFIG_PLL_LF_MODE, config->lfMode); in Cy_SysClk_PllManualConfigure()
1947 …LR_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, (uint32_t)config->outputMode); in Cy_SysClk_PllManualConfigure()
1958 clkPath--; /* to correctly access PLL config and status register structures */ in Cy_SysClk_PllGetConfiguration()
1962 config->feedbackDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, tempReg); in Cy_SysClk_PllGetConfiguration()
1963 config->referenceDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, tempReg); in Cy_SysClk_PllGetConfiguration()
1964 config->outputDiv = (uint8_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, tempReg); in Cy_SysClk_PllGetConfiguration()
1965 config->lfMode = _FLD2BOOL(SRSS_CLK_PLL_CONFIG_PLL_LF_MODE, tempReg); in Cy_SysClk_PllGetConfiguration()
1966 …config->outputMode = (cy_en_fll_pll_output_mode_t)((uint32_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS… in Cy_SysClk_PllGetConfiguration()
1977 clkPath--; /* to correctly access PLL config and status registers structures */ in Cy_SysClk_PllEnable()
1992 timeoutus--) in Cy_SysClk_PllEnable()
2183 { /* PATH or CLKHF */ in Cy_SysClk_StartClkMeasurementCounters()
2188 { /* PATH select */ in Cy_SysClk_StartClkMeasurementCounters()
2216 { /* PATH or CLKHF */ in Cy_SysClk_StartClkMeasurementCounters()
2221 { /* PATH select */ in Cy_SysClk_StartClkMeasurementCounters()
2294 diff = iloFreq - CY_SYSCLK_ILO_TARGET_FREQ; in Cy_SysClk_IloTrim()
2296 else if (iloFreq < (CY_SYSCLK_ILO_TARGET_FREQ - CY_SYSCLK_ILO_TRIM_STEP)) in Cy_SysClk_IloTrim()
2298 diff = CY_SYSCLK_ILO_TARGET_FREQ - iloFreq; in Cy_SysClk_IloTrim()
2320 trim -= diff; in Cy_SysClk_IloTrim()
2327 changeInTrim = (sign ? (int32_t)diff : (0L - (int32_t)diff)); in Cy_SysClk_IloTrim()
2348 diff = piloFreq - CY_SYSCLK_PILO_TARGET_FREQ; in Cy_SysClk_PiloTrim()
2350 else if (piloFreq < (CY_SYSCLK_PILO_TARGET_FREQ - stepSize)) in Cy_SysClk_PiloTrim()
2352 diff = CY_SYSCLK_PILO_TARGET_FREQ - piloFreq; in Cy_SysClk_PiloTrim()
2378 trim -= diff; in Cy_SysClk_PiloTrim()
2389 changeInTrim = ((int32_t)(sign ? (int32_t)diff : (0L - (int32_t)diff))); in Cy_SysClk_PiloTrim()
2435 bitPos--; in Cy_SysClk_PiloInitialTrim()
2479 stepSize += (newFreq - oldFreq); in Cy_SysClk_PiloUpdateTrimStep()
2564 …PLL_OUTPUT_AUTO == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllpll - 1UL])) || in Cy_SysClk_DeepSleepCallback()
2565 …LLPLL_OUTPUT_AUTO1 == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_CONFIG[fllpll - 1UL]))) in Cy_SysClk_DeepSleepCallback()
2570 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllpll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_SysClk_DeepSleepCallback()
2573 /* Change this path source to IMO */ in Cy_SysClk_DeepSleepCallback()
2576 /* Store a record that this path source was changed from ECO */ in Cy_SysClk_DeepSleepCallback()
2611 timeout--; in Cy_SysClk_DeepSleepCallback()
2623 /* Change this path source back to ECO */ in Cy_SysClk_DeepSleepCallback()
2633 timeout--; in Cy_SysClk_DeepSleepCallback()
2640 timeout--; in Cy_SysClk_DeepSleepCallback()
2655 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllpll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_SysClk_DeepSleepCallback()
2659 …CY_REG32_CLR_SET(SRSS_CLK_PLL_CONFIG[fllpll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLP… in Cy_SysClk_DeepSleepCallback()
2674 timeout--; in Cy_SysClk_DeepSleepCallback()
2712 … uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */ in Cy_SysClk_ClkHfGetFrequency() local
2713 uint32_t freq = Cy_SysClk_ClkPathGetFrequency(path); in Cy_SysClk_ClkHfGetFrequency()
2715 /* Divide the path input frequency down and return the result */ in Cy_SysClk_ClkHfGetFrequency()
2824 freq = Cy_SysClk_ClkPathMuxGetFrequency(0UL); /* FLL mapped always to path 0 */ in Cy_SysClk_FllGetFrequency()
2869 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 17.2')
2870 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.6')