Lines Matching refs:spi_periph
67 void spi_i2s_deinit(uint32_t spi_periph) in spi_i2s_deinit() argument
69 switch(spi_periph) { in spi_i2s_deinit()
126 ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) in spi_init() argument
130 reg1 = SPI_CTL0(spi_periph); in spi_init()
133 reg2 = SPI_CTL0(spi_periph); in spi_init()
136 reg3 = SPI_CTL1(spi_periph); in spi_init()
139 if(SPI1 == spi_periph) { in spi_init()
161 SPI_CTL0(spi_periph) = (uint32_t)reg1; in spi_init()
177 SPI_CTL0(spi_periph) = (uint32_t)reg2; in spi_init()
182 SPI_CTL1(spi_periph) = (uint32_t)reg3; in spi_init()
186 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); in spi_init()
197 void spi_enable(uint32_t spi_periph) in spi_enable() argument
199 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; in spi_enable()
208 void spi_disable(uint32_t spi_periph) in spi_disable() argument
210 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); in spi_disable()
236 void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) in i2s_init() argument
239 reg = SPI_I2SCTL(spi_periph); in i2s_init()
252 SPI_I2SCTL(spi_periph) = (uint32_t)reg; in i2s_init()
282 void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32… in i2s_psc_config() argument
294 SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; in i2s_psc_config()
297 if(((uint32_t)spi_periph) == SPI1) { in i2s_psc_config()
351 SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); in i2s_psc_config()
354 SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); in i2s_psc_config()
356 SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; in i2s_psc_config()
365 void i2s_enable(uint32_t spi_periph) in i2s_enable() argument
367 SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; in i2s_enable()
376 void i2s_disable(uint32_t spi_periph) in i2s_disable() argument
378 SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); in i2s_disable()
387 void spi_nss_output_enable(uint32_t spi_periph) in spi_nss_output_enable() argument
389 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; in spi_nss_output_enable()
398 void spi_nss_output_disable(uint32_t spi_periph) in spi_nss_output_disable() argument
400 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); in spi_nss_output_disable()
409 void spi_nss_internal_high(uint32_t spi_periph) in spi_nss_internal_high() argument
411 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; in spi_nss_internal_high()
420 void spi_nss_internal_low(uint32_t spi_periph) in spi_nss_internal_low() argument
422 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); in spi_nss_internal_low()
435 void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) in spi_dma_enable() argument
438 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; in spi_dma_enable()
440 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; in spi_dma_enable()
454 void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) in spi_dma_disable() argument
457 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); in spi_dma_disable()
459 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); in spi_dma_disable()
472 ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) in spi_i2s_data_frame_format_config() argument
475 if(SPI1 == spi_periph){ in spi_i2s_data_frame_format_config()
481 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); in spi_i2s_data_frame_format_config()
483 SPI_CTL0(spi_periph) |= ((uint32_t)frame_format & SPI_FRAMESIZE_MASK); in spi_i2s_data_frame_format_config()
486 reg = SPI_CTL1(spi_periph); in spi_i2s_data_frame_format_config()
491 SPI_CTL1(spi_periph) = reg; in spi_i2s_data_frame_format_config()
503 void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) in spi_i2s_data_transmit() argument
505 SPI_DATA(spi_periph) = (uint32_t)data; in spi_i2s_data_transmit()
514 uint16_t spi_i2s_data_receive(uint32_t spi_periph) in spi_i2s_data_receive() argument
516 return ((uint16_t)SPI_DATA(spi_periph)); in spi_i2s_data_receive()
528 void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) in spi_bidirectional_transfer_config() argument
532 SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; in spi_bidirectional_transfer_config()
535 SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; in spi_bidirectional_transfer_config()
546 void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) in spi_crc_polynomial_set() argument
549 SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; in spi_crc_polynomial_set()
558 uint16_t spi_crc_polynomial_get(uint32_t spi_periph) in spi_crc_polynomial_get() argument
560 return ((uint16_t)SPI_CRCPOLY(spi_periph)); in spi_crc_polynomial_get()
569 void spi_crc_on(uint32_t spi_periph) in spi_crc_on() argument
571 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; in spi_crc_on()
580 void spi_crc_off(uint32_t spi_periph) in spi_crc_off() argument
582 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); in spi_crc_off()
591 void spi_crc_next(uint32_t spi_periph) in spi_crc_next() argument
593 SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; in spi_crc_next()
606 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) in spi_crc_get() argument
609 return ((uint16_t)(SPI_TCRC(spi_periph))); in spi_crc_get()
611 return ((uint16_t)(SPI_RCRC(spi_periph))); in spi_crc_get()
621 void spi_ti_mode_enable(uint32_t spi_periph) in spi_ti_mode_enable() argument
623 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; in spi_ti_mode_enable()
632 void spi_ti_mode_disable(uint32_t spi_periph) in spi_ti_mode_disable() argument
634 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); in spi_ti_mode_disable()
643 void spi_nssp_mode_enable(uint32_t spi_periph) in spi_nssp_mode_enable() argument
645 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; in spi_nssp_mode_enable()
654 void spi_nssp_mode_disable(uint32_t spi_periph) in spi_nssp_mode_disable() argument
656 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); in spi_nssp_mode_disable()
666 void qspi_enable(uint32_t spi_periph) in qspi_enable() argument
668 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; in qspi_enable()
677 void qspi_disable(uint32_t spi_periph) in qspi_disable() argument
679 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); in qspi_disable()
688 void qspi_write_enable(uint32_t spi_periph) in qspi_write_enable() argument
690 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); in qspi_write_enable()
699 void qspi_read_enable(uint32_t spi_periph) in qspi_read_enable() argument
701 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; in qspi_read_enable()
710 void qspi_io23_output_enable(uint32_t spi_periph) in qspi_io23_output_enable() argument
712 SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; in qspi_io23_output_enable()
721 void qspi_io23_output_disable(uint32_t spi_periph) in qspi_io23_output_disable() argument
723 SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); in qspi_io23_output_disable()
736 void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size) in spi_fifo_access_size_config() argument
739 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_BYTEN); in spi_fifo_access_size_config()
741 SPI_CTL1(spi_periph) |= (uint32_t)fifo_access_size; in spi_fifo_access_size_config()
754 void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd) in spi_transmit_odd_config() argument
757 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TXDMA_ODD); in spi_transmit_odd_config()
759 SPI_CTL1(spi_periph) |= (uint32_t)odd; in spi_transmit_odd_config()
772 void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd) in spi_receive_odd_config() argument
775 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RXDMA_ODD); in spi_receive_odd_config()
777 SPI_CTL1(spi_periph) |= (uint32_t)odd; in spi_receive_odd_config()
790 void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length) in spi_crc_length_set() argument
793 SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCL); in spi_crc_length_set()
795 SPI_CTL0(spi_periph) |= (uint32_t)crc_length; in spi_crc_length_set()
810 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) in spi_i2s_interrupt_enable() argument
815 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; in spi_i2s_interrupt_enable()
819 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; in spi_i2s_interrupt_enable()
823 SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; in spi_i2s_interrupt_enable()
842 void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) in spi_i2s_interrupt_disable() argument
847 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); in spi_i2s_interrupt_disable()
851 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); in spi_i2s_interrupt_disable()
855 SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); in spi_i2s_interrupt_disable()
877 FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) in spi_i2s_interrupt_flag_get() argument
879 uint32_t reg1 = SPI_STAT(spi_periph); in spi_i2s_interrupt_flag_get()
880 uint32_t reg2 = SPI_CTL1(spi_periph); in spi_i2s_interrupt_flag_get()
955 FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) in spi_i2s_flag_get() argument
957 if(RESET != (SPI_STAT(spi_periph) & flag)) { in spi_i2s_flag_get()
960 if(SPI1 == spi_periph) { in spi_i2s_flag_get()
963 if(RESET != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)) { in spi_i2s_flag_get()
971 if(RESET != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)) { in spi_i2s_flag_get()
988 void spi_crc_error_clear(uint32_t spi_periph) in spi_crc_error_clear() argument
990 SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); in spi_crc_error_clear()