76 static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};  variable
233         enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;  in enet_initpara_config()
234         enet_initpara.forward_frame = para;  in enet_initpara_config()
238         enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;  in enet_initpara_config()
239         enet_initpara.dmabus_mode = para;  in enet_initpara_config()
243         enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;  in enet_initpara_config()
244         enet_initpara.dma_maxburst = para;  in enet_initpara_config()
248         enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;  in enet_initpara_config()
249         enet_initpara.dma_arbitration = para;  in enet_initpara_config()
253         enet_initpara.option_enable |= (uint32_t)STORE_OPTION;  in enet_initpara_config()
254         enet_initpara.store_forward_mode = para;  in enet_initpara_config()
258         enet_initpara.option_enable |= (uint32_t)DMA_OPTION;  in enet_initpara_config()
264         enet_initpara.dma_function = para;  in enet_initpara_config()
268         enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;  in enet_initpara_config()
269         enet_initpara.vlan_config = para;  in enet_initpara_config()
273         enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;  in enet_initpara_config()
274         enet_initpara.flow_control = para;  in enet_initpara_config()
278         enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;  in enet_initpara_config()
279         enet_initpara.hashtable_high = para;  in enet_initpara_config()
283         enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;  in enet_initpara_config()
284         enet_initpara.hashtable_low = para;  in enet_initpara_config()
288         enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;  in enet_initpara_config()
289         enet_initpara.framesfilter_mode = para;  in enet_initpara_config()
293         enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;  in enet_initpara_config()
294         enet_initpara.halfduplex_param = para;  in enet_initpara_config()
298         enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;  in enet_initpara_config()
299         enet_initpara.timer_config = para;  in enet_initpara_config()
303         enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;  in enet_initpara_config()
304         enet_initpara.interframegap = para;  in enet_initpara_config()
442     if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) {  in enet_init()
443         reg_temp = enet_initpara.forward_frame;  in enet_init()
463     if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) {  in enet_init()
464         temp = enet_initpara.dmabus_mode;  in enet_init()
475     if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) {  in enet_init()
476         temp = enet_initpara.dma_maxburst;  in enet_init()
486     if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) {  in enet_init()
487         temp = enet_initpara.dma_arbitration;  in enet_init()
497     if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) {  in enet_init()
498         temp = enet_initpara.store_forward_mode;  in enet_init()
508     if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) {  in enet_init()
509         reg_temp = enet_initpara.dma_function;  in enet_init()
529     if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) {  in enet_init()
530         reg_temp = enet_initpara.vlan_config;  in enet_init()
540     if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) {  in enet_init()
541         reg_temp = enet_initpara.flow_control;  in enet_init()
563     if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) {  in enet_init()
564         ENET_MAC_HLH = enet_initpara.hashtable_high;  in enet_init()
568     if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) {  in enet_init()
569         ENET_MAC_HLL = enet_initpara.hashtable_low;  in enet_init()
573     if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) {  in enet_init()
574         reg_temp = enet_initpara.framesfilter_mode;  in enet_init()
586     if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) {  in enet_init()
587         reg_temp = enet_initpara.halfduplex_param;  in enet_init()
598     if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) {  in enet_init()
599         reg_temp = enet_initpara.timer_config;  in enet_init()
609     if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) {  in enet_init()
610         reg_temp = enet_initpara.interframegap;  in enet_init()
3413     enet_initpara.option_enable = 0U;  in enet_initpara_reset()
3414     enet_initpara.forward_frame = 0U;  in enet_initpara_reset()
3415     enet_initpara.dmabus_mode = 0U;  in enet_initpara_reset()
3416     enet_initpara.dma_maxburst = 0U;  in enet_initpara_reset()
3417     enet_initpara.dma_arbitration = 0U;  in enet_initpara_reset()
3418     enet_initpara.store_forward_mode = 0U;  in enet_initpara_reset()
3419     enet_initpara.dma_function = 0U;  in enet_initpara_reset()
3420     enet_initpara.vlan_config = 0U;  in enet_initpara_reset()
3421     enet_initpara.flow_control = 0U;  in enet_initpara_reset()
3422     enet_initpara.hashtable_high = 0U;  in enet_initpara_reset()
3423     enet_initpara.hashtable_low = 0U;  in enet_initpara_reset()
3424     enet_initpara.framesfilter_mode = 0U;  in enet_initpara_reset()
3425     enet_initpara.halfduplex_param = 0U;  in enet_initpara_reset()
3426     enet_initpara.timer_config = 0U;  in enet_initpara_reset()
3427     enet_initpara.interframegap = 0U;  in enet_initpara_reset()