Lines Matching +full:fail +full:- +full:fast
5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx
6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx
7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx
8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx
90 …OPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */
91 …uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */
92 …uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */
93 …(uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */
94 …(uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */
95 #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-ne…
96 #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-n…
101 #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioat…
108 … ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */
112 … ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */
189 #define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit…
196 #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet…
198 #define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame ga…
238 #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-q…
243 #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN ta…
430 #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligne…
477 …A_CTL_TSFD BIT(21) /*!< transmit store-and-forward */
479 …MA_CTL_RSFD BIT(25) /*!< receive store-and-forward */
550 … /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */
553 …ffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
557 … BITS(0,31) /*!< transmit frame timestamp low 32-bit value */
560 … BITS(0,31) /*!< transmit frame timestamp high 32-bit value */
579 #define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail…
583 …AFF BIT(30) /*!< destination address filter fail */
594 … /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */
597 …ive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */
612 … BITS(0,31) /*!< receive frame timestamp low 32-bit value */
615 … BITS(0,31) /*!< receive frame timestamp high 32-bit value */
632 #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4…
856 …, /*!< configure the hash list high 32-bit related parameter…
857 …), /*!< configure the hash list low 32-bit related parameter…
868 …ULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */
869 …ALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */
870 …ULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */
871 …ALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */
947 …_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) val…
948 …_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) val…
954 … = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent cloc…
955 … = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clo…
983 … /*!< hash list high 32-bit related parameter…
984 … /*!< hash list low 32-bit related parameter…
1044 …*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */
1050 …D /*!< the MAC disables the reception of frames in half-duplex mode */
1055 … ENET_MAC_CFG_DPM /*!< full-duplex mode enable */
1056 … ((uint32_t)0x00000000U) /*!< half-duplex mode enable */
1075 … /*!< MAC forwards all control frames to application even if they fail the address filter …
1112 … MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= H…
1113 … MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= H…
1114 … MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HC…
1115 … MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HC…
1116 … MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= H…
1132 …((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation fun…
1133 …NET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation fun…
1134 … ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation fun…
1238 … ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP f…
1324 …NABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */
1325 …ISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */
1372 … ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */
1373 … ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */
1379 … ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */
1380 … ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */
1408 … /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */
1450 /* ENET remote wake-up frame register length */
1451 … 8U /*!< remote wake-up frame register len…