Lines Matching refs:CFG1_PLL1MF
710 #define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) macro
711 #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock …
712 #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock …
713 #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock …
714 #define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock …
715 #define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock …
716 #define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock …
717 #define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock …
718 #define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock …
719 #define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock …
720 #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock …