79 static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};  variable
232         enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION;  in enet_initpara_config()
233         enet_initpara.forward_frame = para;  in enet_initpara_config()
237         enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION;  in enet_initpara_config()
238         enet_initpara.dmabus_mode = para;  in enet_initpara_config()
242         enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION;  in enet_initpara_config()
243         enet_initpara.dma_maxburst = para;  in enet_initpara_config()
247         enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION;  in enet_initpara_config()
248         enet_initpara.dma_arbitration = para;  in enet_initpara_config()
252         enet_initpara.option_enable |= (uint32_t)STORE_OPTION;  in enet_initpara_config()
253         enet_initpara.store_forward_mode = para;  in enet_initpara_config()
257         enet_initpara.option_enable |= (uint32_t)DMA_OPTION;  in enet_initpara_config()
263         enet_initpara.dma_function = para;  in enet_initpara_config()
267         enet_initpara.option_enable |= (uint32_t)VLAN_OPTION;  in enet_initpara_config()
268         enet_initpara.vlan_config = para;  in enet_initpara_config()
272         enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION;  in enet_initpara_config()
273         enet_initpara.flow_control = para;  in enet_initpara_config()
277         enet_initpara.option_enable |= (uint32_t)HASHH_OPTION;  in enet_initpara_config()
278         enet_initpara.hashtable_high = para;  in enet_initpara_config()
282         enet_initpara.option_enable |= (uint32_t)HASHL_OPTION;  in enet_initpara_config()
283         enet_initpara.hashtable_low = para;  in enet_initpara_config()
287         enet_initpara.option_enable |= (uint32_t)FILTER_OPTION;  in enet_initpara_config()
288         enet_initpara.framesfilter_mode = para;  in enet_initpara_config()
292         enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION;  in enet_initpara_config()
293         enet_initpara.halfduplex_param = para;  in enet_initpara_config()
297         enet_initpara.option_enable |= (uint32_t)TIMER_OPTION;  in enet_initpara_config()
298         enet_initpara.timer_config = para;   in enet_initpara_config()
302         enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION;  in enet_initpara_config()
303         enet_initpara.interframegap = para;  in enet_initpara_config()
440     if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){  in enet_init()
441         reg_temp = enet_initpara.forward_frame;  in enet_init()
461     if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){  in enet_init()
462         temp = enet_initpara.dmabus_mode;  in enet_init()
473     if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){  in enet_init()
474         temp = enet_initpara.dma_maxburst;  in enet_init()
484     if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){  in enet_init()
485         temp = enet_initpara.dma_arbitration;  in enet_init()
495     if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){  in enet_init()
496         temp = enet_initpara.store_forward_mode;  in enet_init()
506     if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){  in enet_init()
507         reg_temp = enet_initpara.dma_function;  in enet_init()
527     if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){     in enet_init()
528         reg_temp = enet_initpara.vlan_config;  in enet_init()
538     if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){  in enet_init()
539         reg_temp = enet_initpara.flow_control;  in enet_init()
561     if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){  in enet_init()
562         ENET_MAC_HLH = enet_initpara.hashtable_high;  in enet_init()
566     if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){  in enet_init()
567         ENET_MAC_HLL = enet_initpara.hashtable_low;  in enet_init()
571     if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){  in enet_init()
572         reg_temp = enet_initpara.framesfilter_mode;  in enet_init()
584     if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){     in enet_init()
585         reg_temp = enet_initpara.halfduplex_param;  in enet_init()
596     if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){     in enet_init()
597         reg_temp = enet_initpara.timer_config;  in enet_init()
607     if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){  in enet_init()
608         reg_temp = enet_initpara.interframegap;  in enet_init()
3580     enet_initpara.option_enable = 0U;  in enet_initpara_reset()
3581     enet_initpara.forward_frame = 0U;  in enet_initpara_reset()
3582     enet_initpara.dmabus_mode = 0U;  in enet_initpara_reset()
3583     enet_initpara.dma_maxburst = 0U;  in enet_initpara_reset()
3584     enet_initpara.dma_arbitration = 0U;  in enet_initpara_reset()
3585     enet_initpara.store_forward_mode = 0U;  in enet_initpara_reset()
3586     enet_initpara.dma_function = 0U;   in enet_initpara_reset()
3587     enet_initpara.vlan_config = 0U;  in enet_initpara_reset()
3588     enet_initpara.flow_control = 0U;  in enet_initpara_reset()
3589     enet_initpara.hashtable_high = 0U;  in enet_initpara_reset()
3590     enet_initpara.hashtable_low = 0U;  in enet_initpara_reset()
3591     enet_initpara.framesfilter_mode = 0U;  in enet_initpara_reset()
3592     enet_initpara.halfduplex_param = 0U;  in enet_initpara_reset()
3593     enet_initpara.timer_config = 0U;  in enet_initpara_reset()
3594     enet_initpara.interframegap = 0U;  in enet_initpara_reset()