Lines Matching +full:fail +full:- +full:fast
5 \version 2020-03-10, V1.0.0, firmware for GD32E50x
6 \version 2020-08-26, V1.1.0, firmware for GD32E50x
7 \version 2021-03-23, V1.2.0, firmware for GD32E50x
88 …OPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */
89 …uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */
90 …uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */
91 …(uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */
92 …(uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */
93 #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-ne…
94 #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-n…
99 #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioat…
106 … ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */
110 … ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */
187 #define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit…
194 #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet…
196 #define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame ga…
236 #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-q…
241 #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN ta…
426 #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligne…
473 …A_CTL_TSFD BIT(21) /*!< transmit store-and-forward */
475 …MA_CTL_RSFD BIT(25) /*!< receive store-and-forward */
546 … /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */
549 …ffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
553 … BITS(0,31) /*!< transmit frame timestamp low 32-bit value */
556 … BITS(0,31) /*!< transmit frame timestamp high 32-bit value */
575 #define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail…
579 …AFF BIT(30) /*!< destination address filter fail */
590 … /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */
593 …ive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */
608 … BITS(0,31) /*!< receive frame timestamp low 32-bit value */
611 … BITS(0,31) /*!< receive frame timestamp high 32-bit value */
628 #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4…
852 …, /*!< configure the hash list high 32-bit related parameter…
853 …), /*!< configure the hash list low 32-bit related parameter…
864 …ULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */
865 …ALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */
866 …ULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */
867 …ALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */
943 …_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) val…
944 …_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) val…
959 … /*!< hash list high 32-bit related parameter…
960 … /*!< hash list low 32-bit related parameter…
1020 …*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */
1026 …D /*!< the MAC disables the reception of frames in half-duplex mode */
1031 … ENET_MAC_CFG_DPM /*!< full-duplex mode enable */
1032 … ((uint32_t)0x00000000U) /*!< half-duplex mode enable */
1051 … /*!< MAC forwards all control frames to application even if they fail the address filter …
1088 … MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= H…
1089 … MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= H…
1090 … MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HC…
1091 … MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HC…
1092 … MAC_PHY_CTL_CLR(4) /*!< HCLK:150-180 MHz; MDC clock= H…
1108 …((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation fun…
1109 …NET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation fun…
1110 … ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation fun…
1216 … ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP f…
1302 …NABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */
1303 …ISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */
1350 … ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */
1351 … ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */
1357 … ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */
1358 … ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */
1387 … /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */
1433 …= PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent cloc…
1434 … PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clo…
1451 /* ENET remote wake-up frame register length */
1452 … 8U /*!< remote wake-up frame register len…