Lines Matching refs:CTL1_ETSRC
218 #define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) /*!< w… macro
219 #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< T…
220 #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< T…
221 #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< T…
222 #define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< T…
223 #define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< T…
224 #define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< T…
225 #define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< T…
226 #define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< e…
227 #define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< s…
229 #define ADC0_1_EXTTRIG_REGULAR_SHRTIMER_ADCTRG0 (ADC_CTL1_ETSRC4 | CTL1_ETSRC(0)) /*!< S…
230 #define ADC0_1_EXTTRIG_REGULAR_SHRTIMER_ADCTRG2 (ADC_CTL1_ETSRC4 | CTL1_ETSRC(1)) /*!< S…
232 #define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< T…
233 #define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< T…
234 #define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< T…
235 #define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< T…
236 #define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< T…
237 #define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< T…
238 #define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< T…