Lines Matching defs:timerx
60 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control regis… argument
61 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control regis… argument
62 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode co… argument
63 #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and inter… argument
64 #define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt fla… argument
65 #define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software even… argument
66 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel contr… argument
67 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel contr… argument
68 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel contr… argument
69 #define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter regis… argument
70 #define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler reg… argument
71 #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto … argument
72 #define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repet… argument
73 #define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 cap… argument
74 #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 cap… argument
75 #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 cap… argument
76 #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 cap… argument
77 #define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel compl… argument
78 #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configura… argument
79 #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer … argument
80 #define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration… argument