Lines Matching refs:CFG1_PLL2MF
591 #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) macro
592 #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock …
593 #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock …
594 #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock …
595 #define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock …
596 #define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock …
597 #define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock …
598 #define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock …
599 #define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock …
600 #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock …
601 #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock …