Lines Matching refs:CFG1_PLL2MF
725 #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) macro
726 #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock …
727 #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock …
728 #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock …
729 #define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock …
730 #define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock …
731 #define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock …
732 #define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock …
733 #define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock …
734 #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock …
735 #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock …
736 #define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock …
737 #define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock …
738 #define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock …
739 #define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock …
740 #define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock …
741 #define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock …
742 #define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock …
743 #define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock …
744 #define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock …
745 #define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock …
746 #define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock …
747 #define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock …
748 #define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock …
749 #define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock …
750 #define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock …