Lines Matching full:adc
22 * but enabling the SAR ADC as well adds some insurance.) in soc_random_enable()
26 /* Enable SAR ADC to read a disconnected input for additional entropy */ in soc_random_enable()
28 /* Reset ADC clock */ in soc_random_enable()
32 /* Enable clock and select clock source for ADC digital controller */ in soc_random_enable()
39 * Internal ADC sample freq = apb_clk / (APB_SARADC_CLKM_DIV_NUM + 1) / in soc_random_enable()
71 /* Disable ADC filter */ in soc_random_enable()
75 /* Start ADC sample */ in soc_random_enable()
94 /* Power off SAR ADC */ in soc_random_disable()
96 /* return to ADC RTC controller */ in soc_random_disable()
98 /* Invalidate ADC digital trigger timer */ in soc_random_disable()
101 /* Disable ADC digital part */ in soc_random_disable()
103 /* Hold reset bit for ADC digital part */ in soc_random_disable()