Lines Matching refs:REGS
38 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
71 self.REGS = EfuseDefineRegisters
136 self.coding_scheme = self.REGS.CODING_SCHEME_RS
143 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
148 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
164 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
169 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
171 cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD
172 if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0:
173 if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0:
184 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
185 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
192 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)
198 self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000
243 ) = self.REGS.EFUSE_PROGRAMMING_TIMING_PARAMETERS[apb_freq]
245 self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_TSUP_A_M, EFUSE_TSUP_A
248 self.REGS.EFUSE_WR_TIM_CONF0_REG, self.REGS.EFUSE_TPGM_M, EFUSE_TPGM
251 self.REGS.EFUSE_WR_TIM_CONF0_REG, self.REGS.EFUSE_THP_A_M, EFUSE_THP_A
254 self.REGS.EFUSE_WR_TIM_CONF0_REG,
255 self.REGS.EFUSE_TPGM_INACTIVE_M,
263 ) = self.REGS.VDDQ_TIMING_PARAMETERS[apb_freq]
265 self.REGS.EFUSE_DAC_CONF_REG,
266 self.REGS.EFUSE_DAC_CLK_DIV_M,
270 self.REGS.EFUSE_WR_TIM_CONF1_REG,
271 self.REGS.EFUSE_PWR_ON_NUM_M,
275 self.REGS.EFUSE_WR_TIM_CONF2_REG,
276 self.REGS.EFUSE_PWR_OFF_NUM_M,
280 EFUSE_TSUR_A, EFUSE_TRD, EFUSE_THR_A = self.REGS.EFUSE_READING_PARAMETERS[
287 self.REGS.EFUSE_RD_TIM_CONF_REG, self.REGS.EFUSE_TRD_M, EFUSE_TRD
290 self.REGS.EFUSE_RD_TIM_CONF_REG, self.REGS.EFUSE_THR_A_M, EFUSE_THR_A
301 self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4)
310 addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[