Lines Matching refs:REGS
38 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
71 self.REGS = EfuseDefineRegisters
136 self.coding_scheme = self.REGS.CODING_SCHEME_RS
143 "EFUSE_RD_RS_ERR0_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR0_REG)
148 "EFUSE_RD_RS_ERR1_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR1_REG)
164 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
169 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
171 cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD
172 if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0:
173 if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0:
184 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
185 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
192 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)
198 self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000
243 self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF)
245 self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28
248 self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000
251 self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190
260 self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR0_REG + offs * 4)
269 addr_reg_f, fail_bit = self.REGS.BLOCK_FAIL_BIT[block.id]
275 addr_reg_n, num_mask, num_offs = self.REGS.BLOCK_NUM_ERRORS[block.id]