Lines Matching refs:REGS
38 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_RS:
71 self.REGS = EfuseDefineRegisters
133 self.coding_scheme = self.REGS.CODING_SCHEME_RS
140 "EFUSE_RD_RS_ERR_REG", self.read_reg(self.REGS.EFUSE_RD_RS_ERR_REG)
156 self.REGS.EFUSE_PGM_DATA0_REG, self.REGS.EFUSE_PGM_DATA0_REG + 32, 4
161 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
163 cmds = self.REGS.EFUSE_PGM_CMD | self.REGS.EFUSE_READ_CMD
164 if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0:
165 if self.read_reg(self.REGS.EFUSE_CMD_REG) & cmds == 0:
176 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_WRITE_OP_CODE)
177 self.write_reg(self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_PGM_CMD | (block << 2))
184 self.write_reg(self.REGS.EFUSE_CONF_REG, self.REGS.EFUSE_READ_OP_CODE)
190 self.REGS.EFUSE_CMD_REG, self.REGS.EFUSE_READ_CMD, delay_after_us=1000
235 self.update_reg(self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_NUM_M, 0xFF)
237 self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_M, 0x28
240 self.REGS.EFUSE_WR_TIM_CONF1_REG, self.REGS.EFUSE_PWR_ON_NUM_M, 0x3000
243 self.REGS.EFUSE_WR_TIM_CONF2_REG, self.REGS.EFUSE_PWR_OFF_NUM_M, 0x190
248 self.REGS.EFUSE_WR_TIM_CONF0_REG,
249 self.REGS.EFUSE_TPGM_INACTIVE_M,
261 self.read_reg(self.REGS.EFUSE_RD_REPEAT_ERR_REG + offs * 4)
270 addr_reg, err_num_mask, err_num_offs, fail_bit = self.REGS.BLOCK_ERRORS[