Lines Matching refs:REGS
25 parent.coding_scheme = parent.REGS.CODING_SCHEME_NONE
33 if self.get_coding_scheme() == self.parent.REGS.CODING_SCHEME_34:
81 self.REGS = EfuseDefineRegisters
110 if self.coding_scheme == self.REGS.CODING_SCHEME_NONE:
115 elif self.coding_scheme == self.REGS.CODING_SCHEME_34:
168 self.read_efuse(self.REGS.EFUSE_CODING_SCHEME_WORD)
169 & self.REGS.EFUSE_CODING_SCHEME_MASK
171 if coding_scheme == self.REGS.CODING_SCHEME_NONE_RECOVERY:
172 self.coding_scheme = self.REGS.CODING_SCHEME_NONE
180 "EFUSE_REG_DEC_STATUS", self.read_reg(self.REGS.EFUSE_REG_DEC_STATUS)
191 clk_sel0, clk_sel1, dac_clk_div = self.REGS.EFUSE_CLK_SETTINGS[apb_freq]
194 self.REGS.EFUSE_DAC_CONF_REG, self.REGS.EFUSE_DAC_CLK_DIV_MASK, dac_clk_div
197 self.REGS.EFUSE_CLK_REG, self.REGS.EFUSE_CLK_SEL0_MASK, clk_sel0
200 self.REGS.EFUSE_CLK_REG, self.REGS.EFUSE_CLK_SEL1_MASK, clk_sel1
203 self.write_reg(self.REGS.EFUSE_REG_CONF, self.REGS.EFUSE_CONF_WRITE)
204 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_WRITE)
210 deadline = time.time() + self.REGS.EFUSE_BURN_TIMEOUT
212 if self.read_reg(self.REGS.EFUSE_REG_CMD) == 0:
220 self.write_reg(self.REGS.EFUSE_REG_CONF, self.REGS.EFUSE_CONF_READ)
221 self.write_reg(self.REGS.EFUSE_REG_CMD, self.REGS.EFUSE_CMD_READ)
229 self.read_reg(self.REGS.EFUSE_REG_DEC_STATUS)
230 & self.REGS.EFUSE_REG_DEC_STATUS_MASK
385 apb_ctl_date = self.parent.read_reg(self.parent.REGS.APB_CTL_DATE_ADDR)
387 apb_ctl_date >> self.parent.REGS.APB_CTL_DATE_S
388 ) & self.parent.REGS.APB_CTL_DATE_V