Lines Matching refs:chip
8 These options control how many I/O pins are used for communication with the attached SPI flash chip…
10 …g or executing code and data from the SPI flash chip. Data is read and then cached internally to t…
55 …Each read command and the read address is sent from the host to the flash chip via normal SPI, but…
58 …command is sent from the host to the flash chip via normal SPI, but then the address is sent to th…
63 Consult the datasheet for your particular SPI flash chip to determine if it supports either or both…
68 … SPI" mode. This mode added two additional pins (otherwise used for flash chip ``WP`` and ``HOLD``…
70 …PI modes, and not all ESP chips have these pins wired up to the SPI flash chip. Some flash chips r…
80 Why don't qio & qout modes work with my Espressif chip/module?
85 * The WP and HOLD pins of the SPI flash chip are not wired to the correct GPIOs of the Espressif ch…
86 … SPI flash chip does not support quad modes. Look up the flash chip datasheet to see which modes i…
87 …is not enabled correctly for this chip model. SPI flash is not a standard, so every manufacturer i…
88 …pressif chips, this often means that the chip first boots in a Dual SPI mode and then software det…
89 …If the particular chip model is not supported by the software then it won't be able to enter quad …
94 Some SPI flash chip models only support the "Dual Output Fast Read" and/or "Quad Output Fast Read" …
104 How is flash mode communicated to the Espressif chip?
113 When ROM code boots this bootloader from flash, the bootloader software checks the flash chip model…
114 This is because of the multiple different ways to enable Quad SPI on different chip models.