63 #define XTENSA_DBREGN_A(n)		(0x0000+(n))	/* address registers a0..a15 */  argument
64 #define XTENSA_DBREGN_B(n)		(0x0010+(n))	/* boolean bits b0..b15 */  argument
67 #define XTENSA_DBREGN_BO(n)		(0x0022+(n))	/* boolean octuple-bits bo0..bo1 */  argument
68 #define XTENSA_DBREGN_BQ(n)		(0x0024+(n))	/* boolean quadruple-bits bq0..bq3 */  argument
69 #define XTENSA_DBREGN_BD(n)		(0x0028+(n))	/* boolean double-bits bd0..bd7 */  argument
70 #define XTENSA_DBREGN_F(n)		(0x0030+(n))	/* floating point registers f0..f15 */  argument
71 #define XTENSA_DBREGN_VEC(n)		(0x0040+(n))	/* Vectra vec regs v0..v15 */  argument
72 #define XTENSA_DBREGN_VSEL(n)		(0x0050+(n))	/* Vectra sel s0..s3 (V1) ..s7 (V2) */  argument
73 #define XTENSA_DBREGN_VALIGN(n)		(0x0058+(n))	/* Vectra valign regs u0..u3 */  argument
74 #define XTENSA_DBREGN_VCOEFF(n)		(0x005C+(n))	/* Vectra I vcoeff regs c0..c1 */  argument
76 #define XTENSA_DBREGN_AEP(n)		(0x0060+(n))	/* HiFi2 Audio Engine regs aep0..aep7 */  argument
77 #define XTENSA_DBREGN_AEQ(n)		(0x0068+(n))	/* HiFi2 Audio Engine regs aeq0..aeq3 */  argument
79 #define XTENSA_DBREGN_AR(n)		(0x0100+(n))	/* physical address regs ar0..ar63  argument
82 #define XTENSA_DBREGN_SREG(n)		(0x0200+(n))	/* special registers 0..255 (core) */  argument
84 #define XTENSA_DBREGN_MR(n)		XTENSA_DBREGN_SREG(0x20+(n))	/* MAC16 registers m0..m3 */  argument
85 #define XTENSA_DBREGN_UREG(n)		(0x0300+(n))	/* user registers 0..255 (TIE) */  argument
89 #define XTENSA_DBREGN_DBAGENT(n)	(0xF000+(n))	/* non-processor "registers" 0..4095 for  argument