Lines Matching refs:slot_cfg
109 …s_hal_std_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg) in i2s_hal_std_set_tx_slot() argument
111 uint32_t slot_bit_width = (int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width ? in i2s_hal_std_set_tx_slot()
112 slot_cfg->data_bit_width : slot_cfg->slot_bit_width; in i2s_hal_std_set_tx_slot()
115 i2s_ll_tx_set_sample_bit(hal->dev, slot_bit_width, slot_cfg->data_bit_width); in i2s_hal_std_set_tx_slot()
116 i2s_ll_tx_enable_msb_shift(hal->dev, slot_cfg->std.bit_shift); in i2s_hal_std_set_tx_slot()
117 i2s_ll_tx_set_ws_width(hal->dev, slot_cfg->std.ws_width); in i2s_hal_std_set_tx_slot()
119 i2s_ll_tx_enable_mono_mode(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_MONO); in i2s_hal_std_set_tx_slot()
120 …i2s_ll_tx_select_std_slot(hal->dev, slot_cfg->std.slot_mask, slot_cfg->slot_mode == I2S_SLOT_MODE_… in i2s_hal_std_set_tx_slot()
122 i2s_ll_tx_enable_msb_right(hal->dev, slot_cfg->std.msb_right); in i2s_hal_std_set_tx_slot()
123 i2s_ll_tx_enable_right_first(hal->dev, slot_cfg->std.ws_pol); in i2s_hal_std_set_tx_slot()
127 …bool is_copy_mono = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO && slot_cfg->std.slot_mask == I2S_ST… in i2s_hal_std_set_tx_slot()
129 i2s_ll_tx_select_std_slot(hal->dev, is_copy_mono ? I2S_STD_SLOT_LEFT : slot_cfg->std.slot_mask); in i2s_hal_std_set_tx_slot()
130 i2s_ll_tx_set_skip_mask(hal->dev, (slot_cfg->std.slot_mask != I2S_STD_SLOT_BOTH) && in i2s_hal_std_set_tx_slot()
131 (slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO)); in i2s_hal_std_set_tx_slot()
133 i2s_ll_tx_set_ws_idle_pol(hal->dev, slot_cfg->std.ws_pol); in i2s_hal_std_set_tx_slot()
134 i2s_ll_tx_set_bit_order(hal->dev, slot_cfg->std.bit_order_lsb); in i2s_hal_std_set_tx_slot()
135 i2s_ll_tx_enable_left_align(hal->dev, slot_cfg->std.left_align); in i2s_hal_std_set_tx_slot()
136 i2s_ll_tx_enable_big_endian(hal->dev, slot_cfg->std.big_endian); in i2s_hal_std_set_tx_slot()
140 …s_hal_std_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg) in i2s_hal_std_set_rx_slot() argument
142 uint32_t slot_bit_width = (int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width ? in i2s_hal_std_set_rx_slot()
143 slot_cfg->data_bit_width : slot_cfg->slot_bit_width; in i2s_hal_std_set_rx_slot()
146 i2s_ll_rx_set_sample_bit(hal->dev, slot_bit_width, slot_cfg->data_bit_width); in i2s_hal_std_set_rx_slot()
147 i2s_ll_rx_enable_mono_mode(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_MONO); in i2s_hal_std_set_rx_slot()
148 i2s_ll_rx_enable_msb_shift(hal->dev, slot_cfg->std.bit_shift); in i2s_hal_std_set_rx_slot()
149 i2s_ll_rx_set_ws_width(hal->dev, slot_cfg->std.ws_width); in i2s_hal_std_set_rx_slot()
151 i2s_ll_rx_select_std_slot(hal->dev, slot_cfg->std.slot_mask, slot_cfg->std.msb_right); in i2s_hal_std_set_rx_slot()
152 i2s_ll_rx_enable_msb_right(hal->dev, slot_cfg->std.msb_right); in i2s_hal_std_set_rx_slot()
153 i2s_ll_rx_enable_right_first(hal->dev, slot_cfg->std.ws_pol); in i2s_hal_std_set_rx_slot()
157 i2s_ll_rx_select_std_slot(hal->dev, slot_cfg->std.slot_mask); in i2s_hal_std_set_rx_slot()
159 i2s_ll_rx_set_ws_idle_pol(hal->dev, slot_cfg->std.ws_pol); in i2s_hal_std_set_rx_slot()
160 i2s_ll_rx_set_bit_order(hal->dev, slot_cfg->std.bit_order_lsb); in i2s_hal_std_set_rx_slot()
161 i2s_ll_rx_enable_left_align(hal->dev, slot_cfg->std.left_align); in i2s_hal_std_set_rx_slot()
162 i2s_ll_rx_enable_big_endian(hal->dev, slot_cfg->std.big_endian); in i2s_hal_std_set_rx_slot()
180 …s_hal_pdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg) in i2s_hal_pdm_set_tx_slot() argument
182 bool is_mono = slot_cfg->slot_mode == I2S_SLOT_MODE_MONO; in i2s_hal_pdm_set_tx_slot()
187 i2s_ll_tx_set_pdm_prescale(hal->dev, slot_cfg->pdm_tx.sd_prescale); in i2s_hal_pdm_set_tx_slot()
188 i2s_ll_tx_set_pdm_hp_scale(hal->dev, slot_cfg->pdm_tx.hp_scale); in i2s_hal_pdm_set_tx_slot()
189 i2s_ll_tx_set_pdm_lp_scale(hal->dev, slot_cfg->pdm_tx.lp_scale); in i2s_hal_pdm_set_tx_slot()
190 i2s_ll_tx_set_pdm_sinc_scale(hal->dev, slot_cfg->pdm_tx.sinc_scale); in i2s_hal_pdm_set_tx_slot()
191 i2s_ll_tx_set_pdm_sd_scale(hal->dev, slot_cfg->pdm_tx.sd_scale); in i2s_hal_pdm_set_tx_slot()
194 uint32_t slot_bit_width = (int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width ? in i2s_hal_pdm_set_tx_slot()
195 slot_cfg->data_bit_width : slot_cfg->slot_bit_width; in i2s_hal_pdm_set_tx_slot()
197 i2s_ll_tx_set_sample_bit(hal->dev, slot_bit_width, slot_cfg->data_bit_width); in i2s_hal_pdm_set_tx_slot()
199 i2s_ll_tx_select_pdm_slot(hal->dev, slot_cfg->pdm_tx.slot_mask & I2S_STD_SLOT_BOTH, is_mono); in i2s_hal_pdm_set_tx_slot()
204 i2s_ll_tx_pdm_line_mode(hal->dev, slot_cfg->pdm_tx.line_mode); in i2s_hal_pdm_set_tx_slot()
216 float expt_cut_off = slot_cfg->pdm_tx.hp_cut_off_freq_hz; in i2s_hal_pdm_set_tx_slot()
225 i2s_ll_tx_enable_pdm_hp_filter(hal->dev, slot_cfg->pdm_tx.hp_en); in i2s_hal_pdm_set_tx_slot()
228 i2s_ll_tx_set_pdm_sd_dither(hal->dev, slot_cfg->pdm_tx.sd_dither); in i2s_hal_pdm_set_tx_slot()
229 i2s_ll_tx_set_pdm_sd_dither2(hal->dev, slot_cfg->pdm_tx.sd_dither2); in i2s_hal_pdm_set_tx_slot()
240 …s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg) in i2s_hal_pdm_set_rx_slot() argument
242 uint32_t slot_bit_width = (int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width ? in i2s_hal_pdm_set_rx_slot()
243 slot_cfg->data_bit_width : slot_cfg->slot_bit_width; in i2s_hal_pdm_set_rx_slot()
246 i2s_ll_rx_set_sample_bit(hal->dev, slot_bit_width, slot_cfg->data_bit_width); in i2s_hal_pdm_set_rx_slot()
248 i2s_ll_rx_enable_mono_mode(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_MONO); in i2s_hal_pdm_set_rx_slot()
249 i2s_ll_rx_select_pdm_slot(hal->dev, slot_cfg->pdm_rx.slot_mask); in i2s_hal_pdm_set_rx_slot()
257 …uint32_t slot_mask = (slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO && slot_cfg->pdm_rx.slot_mask <=… in i2s_hal_pdm_set_rx_slot()
258 I2S_PDM_SLOT_BOTH : slot_cfg->pdm_rx.slot_mask; in i2s_hal_pdm_set_rx_slot()
261 …uint32_t slot_mask = slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO ? I2S_PDM_SLOT_BOTH : slot_cfg->p… in i2s_hal_pdm_set_rx_slot()
277 …s_hal_tdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg) in i2s_hal_tdm_set_tx_slot() argument
279 uint32_t slot_bit_width = (int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width ? in i2s_hal_tdm_set_tx_slot()
280 slot_cfg->data_bit_width : slot_cfg->slot_bit_width; in i2s_hal_tdm_set_tx_slot()
282 uint32_t msk = slot_cfg->tdm.slot_mask; in i2s_hal_tdm_set_tx_slot()
286 cnt = ((cnt < 2) && (slot_cfg->tdm.ws_width != 1)) ? 2 : cnt; in i2s_hal_tdm_set_tx_slot()
287 uint32_t total_slot = slot_cfg->tdm.total_slot > cnt ? slot_cfg->tdm.total_slot : cnt; in i2s_hal_tdm_set_tx_slot()
290 i2s_ll_tx_set_sample_bit(hal->dev, slot_bit_width, slot_cfg->data_bit_width); in i2s_hal_tdm_set_tx_slot()
291 i2s_ll_tx_enable_mono_mode(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_MONO); in i2s_hal_tdm_set_tx_slot()
292 i2s_ll_tx_enable_msb_shift(hal->dev, slot_cfg->tdm.bit_shift); in i2s_hal_tdm_set_tx_slot()
293 if (slot_cfg->tdm.ws_width == 0) { // 0: I2S_TDM_AUTO_WS_WIDTH in i2s_hal_tdm_set_tx_slot()
296 i2s_ll_tx_set_ws_width(hal->dev, slot_cfg->tdm.ws_width); in i2s_hal_tdm_set_tx_slot()
299 i2s_ll_tx_set_ws_idle_pol(hal->dev, slot_cfg->tdm.ws_pol); in i2s_hal_tdm_set_tx_slot()
302 i2s_ll_tx_set_active_chan_mask(hal->dev, (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ? in i2s_hal_tdm_set_tx_slot()
303 I2S_TDM_SLOT0 : (uint32_t)slot_cfg->tdm.slot_mask); in i2s_hal_tdm_set_tx_slot()
304 i2s_ll_tx_set_skip_mask(hal->dev, slot_cfg->tdm.skip_mask); in i2s_hal_tdm_set_tx_slot()
306 i2s_ll_tx_set_bit_order(hal->dev, slot_cfg->tdm.bit_order_lsb); in i2s_hal_tdm_set_tx_slot()
307 i2s_ll_tx_enable_left_align(hal->dev, slot_cfg->tdm.left_align); in i2s_hal_tdm_set_tx_slot()
308 i2s_ll_tx_enable_big_endian(hal->dev, slot_cfg->tdm.big_endian); in i2s_hal_tdm_set_tx_slot()
311 …s_hal_tdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_hal_slot_config_t *slot_cfg) in i2s_hal_tdm_set_rx_slot() argument
313 uint32_t slot_bit_width = (int)slot_cfg->slot_bit_width < (int)slot_cfg->data_bit_width ? in i2s_hal_tdm_set_rx_slot()
314 slot_cfg->data_bit_width : slot_cfg->slot_bit_width; in i2s_hal_tdm_set_rx_slot()
316 uint32_t msk = slot_cfg->tdm.slot_mask; in i2s_hal_tdm_set_rx_slot()
320 cnt = ((cnt < 2) && (slot_cfg->tdm.ws_width != 1)) ? 2 : cnt; in i2s_hal_tdm_set_rx_slot()
321 uint32_t total_slot = slot_cfg->tdm.total_slot > cnt ? slot_cfg->tdm.total_slot : cnt; in i2s_hal_tdm_set_rx_slot()
324 i2s_ll_rx_set_sample_bit(hal->dev, slot_bit_width, slot_cfg->data_bit_width); in i2s_hal_tdm_set_rx_slot()
325 i2s_ll_rx_enable_mono_mode(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_MONO); in i2s_hal_tdm_set_rx_slot()
326 i2s_ll_rx_enable_msb_shift(hal->dev, slot_cfg->tdm.bit_shift); in i2s_hal_tdm_set_rx_slot()
327 if (slot_cfg->tdm.ws_width == 0) { // 0: I2S_TDM_AUTO_WS_WIDTH in i2s_hal_tdm_set_rx_slot()
330 i2s_ll_rx_set_ws_width(hal->dev, slot_cfg->tdm.ws_width); in i2s_hal_tdm_set_rx_slot()
333 i2s_ll_rx_set_ws_idle_pol(hal->dev, slot_cfg->tdm.ws_pol); in i2s_hal_tdm_set_rx_slot()
336 i2s_ll_rx_set_active_chan_mask(hal->dev, (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ? in i2s_hal_tdm_set_rx_slot()
337 I2S_TDM_SLOT0 : (uint32_t)slot_cfg->tdm.slot_mask); in i2s_hal_tdm_set_rx_slot()
339 i2s_ll_rx_set_bit_order(hal->dev, slot_cfg->tdm.bit_order_lsb); in i2s_hal_tdm_set_rx_slot()
340 i2s_ll_rx_enable_left_align(hal->dev, slot_cfg->tdm.left_align); in i2s_hal_tdm_set_rx_slot()
341 i2s_ll_rx_enable_big_endian(hal->dev, slot_cfg->tdm.big_endian); in i2s_hal_tdm_set_rx_slot()