466     hw->wakeup.cntl0.sleep_req = 1;  in pmu_ll_hp_set_sleep_enable()
471     hw->wakeup.cntl1.sleep_reject_ena = reject;  in pmu_ll_hp_set_reject_enable()
472     hw->wakeup.cntl1.slp_reject_en = 1;  in pmu_ll_hp_set_reject_enable()
477     hw->wakeup.cntl1.slp_reject_en = 0;  in pmu_ll_hp_set_reject_disable()
480 FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)  in pmu_ll_hp_set_wakeup_enable()  argument
482     hw->wakeup.cntl2 = wakeup;  in pmu_ll_hp_set_wakeup_enable()
487     hw->wakeup.cntl3.sleep_prt_sel = mode;  in pmu_ll_hp_set_sleep_protect_mode()
492     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);  in pmu_ll_hp_set_min_sleep_cycle()
497     hw->wakeup.cntl4.slp_reject_cause_clr = 1;  in pmu_ll_hp_clear_reject_cause()
502     return (hw->hp_ext.int_raw.wakeup == 1);  in pmu_ll_hp_is_sleep_wakeup()
517     hw->hp_ext.int_clr.wakeup = 1;  in pmu_ll_hp_clear_wakeup_intr_status()
527     return hw->wakeup.status0;  in pmu_ll_hp_get_wakeup_cause()
532     return hw->wakeup.status1;  in pmu_ll_hp_get_reject_cause()
547     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);  in pmu_ll_lp_set_min_sleep_cycle()
592     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);  in pmu_ll_lp_set_analog_wait_target_cycle()
597     return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);  in pmu_ll_lp_get_analog_wait_target_cycle()
602     hw->wakeup.cntl5.modem_wait_target = cycle;  in pmu_ll_set_modem_wait_target_cycle()
607     return hw->wakeup.cntl5.modem_wait_target;  in pmu_ll_get_modem_wait_target_cycle()
652     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);  in pmu_ll_hp_set_analog_wait_target_cycle()
657     return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);  in pmu_ll_hp_get_analog_wait_target_cycle()