179     hal->tx_desc = (eth_dma_tx_descriptor_t *)((uint32_t)hal->descriptors +  in emac_hal_reset_desc_chain()
201         hal->tx_desc[i].TDES0.Own = EMAC_LL_DMADESC_OWNER_CPU;  in emac_hal_reset_desc_chain()
202         hal->tx_desc[i].TDES0.SecondAddressChained = 1;  in emac_hal_reset_desc_chain()
203         hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;  in emac_hal_reset_desc_chain()
205         hal->tx_desc[1].TDES0.InterruptOnComplete = 1;  in emac_hal_reset_desc_chain()
207         hal->tx_desc[i].TDES0.TransmitTimestampEnable = 1;  in emac_hal_reset_desc_chain()
209         hal->tx_desc[i].Buffer1Addr = (uint32_t)(hal->tx_buf[i]);  in emac_hal_reset_desc_chain()
211         hal->tx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc + i + 1);  in emac_hal_reset_desc_chain()
214     hal->tx_desc[CONFIG_ETH_DMA_TX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc);  in emac_hal_reset_desc_chain()
218     emac_ll_set_tx_desc_addr(hal->dma_regs, (uint32_t)hal->tx_desc);  in emac_hal_reset_desc_chain()
425     eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc;  in emac_hal_transmit_frame()
463         hal->tx_desc->TDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;  in emac_hal_transmit_frame()
464         hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);  in emac_hal_transmit_frame()
481     eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc;  in emac_hal_transmit_multiple_buf_frame()
551         hal->tx_desc->TDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;  in emac_hal_transmit_multiple_buf_frame()
552         hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr);  in emac_hal_transmit_multiple_buf_frame()