178     hal->rx_desc = (eth_dma_rx_descriptor_t *)(hal->descriptors);  in emac_hal_reset_desc_chain()
184         hal->rx_desc[i].RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;  in emac_hal_reset_desc_chain()
186         hal->rx_desc[i].RDES1.SecondAddressChained = 1;  in emac_hal_reset_desc_chain()
187         hal->rx_desc[i].RDES1.ReceiveBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;  in emac_hal_reset_desc_chain()
189         hal->rx_desc[i].RDES1.DisableInterruptOnComplete = 0;  in emac_hal_reset_desc_chain()
191         hal->rx_desc[i].Buffer1Addr = (uint32_t)(hal->rx_buf[i]);  in emac_hal_reset_desc_chain()
193         hal->rx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc + i + 1);  in emac_hal_reset_desc_chain()
196     hal->rx_desc[CONFIG_ETH_DMA_RX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc);  in emac_hal_reset_desc_chain()
217     emac_ll_set_rx_desc_addr(hal->dma_regs, (uint32_t)hal->rx_desc);  in emac_hal_reset_desc_chain()
562     eth_dma_rx_descriptor_t *desc_iter = hal->rx_desc;  in emac_hal_alloc_recv_buf()
601     eth_dma_rx_descriptor_t *desc_iter = hal->rx_desc;  in emac_hal_receive_frame()
602     eth_dma_rx_descriptor_t *first_desc = hal->rx_desc;  in emac_hal_receive_frame()
668         hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);  in emac_hal_receive_frame()
680     eth_dma_rx_descriptor_t *desc_iter = hal->rx_desc;  in emac_hal_flush_recv_frame()
681     eth_dma_rx_descriptor_t *first_desc = hal->rx_desc;  in emac_hal_flush_recv_frame()
725         hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);  in emac_hal_flush_recv_frame()