Lines Matching refs:hal
26 static esp_err_t emac_hal_flush_trans_fifo(emac_hal_context_t *hal) in emac_hal_flush_trans_fifo() argument
28 emac_ll_flush_trans_fifo_enable(hal->dma_regs, true); in emac_hal_flush_trans_fifo()
31 if (emac_ll_get_flush_trans_fifo(hal->dma_regs) == 0) { in emac_hal_flush_trans_fifo()
146 void emac_hal_init(emac_hal_context_t *hal, void *descriptors, in emac_hal_init() argument
149 hal->dma_regs = &EMAC_DMA; in emac_hal_init()
150 hal->mac_regs = &EMAC_MAC; in emac_hal_init()
151 hal->ext_regs = &EMAC_EXT; in emac_hal_init()
152 hal->descriptors = descriptors; in emac_hal_init()
153 hal->rx_buf = rx_buf; in emac_hal_init()
154 hal->tx_buf = tx_buf; in emac_hal_init()
157 void emac_hal_set_csr_clock_range(emac_hal_context_t *hal, int freq) in emac_hal_set_csr_clock_range() argument
161 emac_ll_set_csr_clock_division(hal->mac_regs, 2); // CSR clock/16 in emac_hal_set_csr_clock_range()
163 emac_ll_set_csr_clock_division(hal->mac_regs, 3); // CSR clock/26 in emac_hal_set_csr_clock_range()
165 emac_ll_set_csr_clock_division(hal->mac_regs, 0); // CSR clock/42 in emac_hal_set_csr_clock_range()
167 emac_ll_set_csr_clock_division(hal->mac_regs, 1); // CSR clock/62 in emac_hal_set_csr_clock_range()
169 emac_ll_set_csr_clock_division(hal->mac_regs, 4); // CSR clock/102 in emac_hal_set_csr_clock_range()
171 emac_ll_set_csr_clock_division(hal->mac_regs, 5); // CSR clock/124 in emac_hal_set_csr_clock_range()
175 void emac_hal_reset_desc_chain(emac_hal_context_t *hal) in emac_hal_reset_desc_chain() argument
178 hal->rx_desc = (eth_dma_rx_descriptor_t *)(hal->descriptors); in emac_hal_reset_desc_chain()
179 hal->tx_desc = (eth_dma_tx_descriptor_t *)((uint32_t)hal->descriptors + in emac_hal_reset_desc_chain()
184 hal->rx_desc[i].RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA; in emac_hal_reset_desc_chain()
186 hal->rx_desc[i].RDES1.SecondAddressChained = 1; in emac_hal_reset_desc_chain()
187 hal->rx_desc[i].RDES1.ReceiveBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE; in emac_hal_reset_desc_chain()
189 hal->rx_desc[i].RDES1.DisableInterruptOnComplete = 0; in emac_hal_reset_desc_chain()
191 hal->rx_desc[i].Buffer1Addr = (uint32_t)(hal->rx_buf[i]); in emac_hal_reset_desc_chain()
193 hal->rx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc + i + 1); in emac_hal_reset_desc_chain()
196 hal->rx_desc[CONFIG_ETH_DMA_RX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->rx_desc); in emac_hal_reset_desc_chain()
201 hal->tx_desc[i].TDES0.Own = EMAC_LL_DMADESC_OWNER_CPU; in emac_hal_reset_desc_chain()
202 hal->tx_desc[i].TDES0.SecondAddressChained = 1; in emac_hal_reset_desc_chain()
203 hal->tx_desc[i].TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE; in emac_hal_reset_desc_chain()
205 hal->tx_desc[1].TDES0.InterruptOnComplete = 1; in emac_hal_reset_desc_chain()
207 hal->tx_desc[i].TDES0.TransmitTimestampEnable = 1; in emac_hal_reset_desc_chain()
209 hal->tx_desc[i].Buffer1Addr = (uint32_t)(hal->tx_buf[i]); in emac_hal_reset_desc_chain()
211 hal->tx_desc[i].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc + i + 1); in emac_hal_reset_desc_chain()
214 hal->tx_desc[CONFIG_ETH_DMA_TX_BUFFER_NUM - 1].Buffer2NextDescAddr = (uint32_t)(hal->tx_desc); in emac_hal_reset_desc_chain()
217 emac_ll_set_rx_desc_addr(hal->dma_regs, (uint32_t)hal->rx_desc); in emac_hal_reset_desc_chain()
218 emac_ll_set_tx_desc_addr(hal->dma_regs, (uint32_t)hal->tx_desc); in emac_hal_reset_desc_chain()
221 void emac_hal_init_mac_default(emac_hal_context_t *hal) in emac_hal_init_mac_default() argument
225 emac_ll_watchdog_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
227 emac_ll_jabber_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
229 emac_ll_set_inter_frame_gap(hal->mac_regs, EMAC_LL_INTERFRAME_GAP_96BIT); in emac_hal_init_mac_default()
231 emac_ll_carrier_sense_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
233 emac_ll_set_port_speed(hal->mac_regs, ETH_SPEED_100M);; in emac_hal_init_mac_default()
235 emac_ll_recv_own_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
237 emac_ll_loopback_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
239 emac_ll_set_duplex(hal->mac_regs, ETH_DUPLEX_FULL); in emac_hal_init_mac_default()
241 emac_ll_checksum_offload_mode(hal->mac_regs, ETH_CHECKSUM_HW); in emac_hal_init_mac_default()
243 emac_ll_retry_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
245 emac_ll_auto_pad_crc_strip_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
247 emac_ll_set_back_off_limit(hal->mac_regs, EMAC_LL_BACKOFF_LIMIT_10); in emac_hal_init_mac_default()
249 emac_ll_deferral_check_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
251 emac_ll_set_preamble_length(hal->mac_regs, EMAC_LL_PREAMBLE_LENGTH_7); in emac_hal_init_mac_default()
255 emac_ll_receive_all_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
257 emac_ll_set_src_addr_filter(hal->mac_regs, EMAC_LL_SOURCE_ADDR_FILTER_DISABLE); in emac_hal_init_mac_default()
258 emac_ll_sa_inverse_filter_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
260 emac_ll_set_pass_ctrl_frame_mode(hal->mac_regs, EMAC_LL_CONTROL_FRAME_BLOCKALL); in emac_hal_init_mac_default()
262 emac_ll_broadcast_frame_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
263 emac_ll_pass_all_multicast_enable(hal->mac_regs, true); in emac_hal_init_mac_default()
265 emac_ll_da_inverse_filter_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
267 emac_ll_promiscuous_mode_enable(hal->mac_regs, false); in emac_hal_init_mac_default()
270 void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable) in emac_hal_enable_flow_ctrl() argument
275 emac_ll_set_pause_time(hal->mac_regs, EMAC_LL_PAUSE_TIME); in emac_hal_enable_flow_ctrl()
277 emac_ll_zero_quanta_pause_enable(hal->mac_regs, true); in emac_hal_enable_flow_ctrl()
279 emac_ll_set_pause_low_threshold(hal->mac_regs, EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_28); in emac_hal_enable_flow_ctrl()
281 emac_ll_unicast_pause_frame_detect_enable(hal->mac_regs, false); in emac_hal_enable_flow_ctrl()
283 emac_ll_receive_flow_ctrl_enable(hal->mac_regs, true); in emac_hal_enable_flow_ctrl()
285 emac_ll_transmit_flow_ctrl_enable(hal->mac_regs, true); in emac_hal_enable_flow_ctrl()
287 emac_ll_clear(hal->mac_regs); in emac_hal_enable_flow_ctrl()
291 void emac_hal_init_dma_default(emac_hal_context_t *hal, emac_hal_dma_config_t *hal_config) in emac_hal_init_dma_default() argument
295 emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
297 emac_ll_recv_store_forward_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
299 emac_ll_flush_recv_frame_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
301 emac_ll_trans_store_forward_enable(hal->dma_regs, false); in emac_hal_init_dma_default()
303 emac_hal_flush_trans_fifo(hal); in emac_hal_init_dma_default()
305 emac_ll_set_transmit_threshold(hal->dma_regs, EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_64); in emac_hal_init_dma_default()
307 emac_ll_forward_err_frame_enable(hal->dma_regs, false); in emac_hal_init_dma_default()
309 emac_ll_forward_undersized_good_frame_enable(hal->dma_regs, false); in emac_hal_init_dma_default()
311 emac_ll_set_recv_threshold(hal->dma_regs, EMAC_LL_RECEIVE_THRESHOLD_CONTROL_64); in emac_hal_init_dma_default()
313 emac_ll_opt_second_frame_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
317 emac_ll_mixed_burst_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
319 emac_ll_addr_align_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
321 emac_ll_use_separate_pbl_enable(hal->dma_regs, false); in emac_hal_init_dma_default()
323 emac_ll_set_prog_burst_len(hal->dma_regs, hal_config->dma_burst_len); in emac_hal_init_dma_default()
325 emac_ll_enhance_desc_enable(hal->dma_regs, true); in emac_hal_init_dma_default()
327 emac_ll_set_desc_skip_len(hal->dma_regs, 0); in emac_hal_init_dma_default()
329 emac_ll_fixed_arbitration_enable(hal->dma_regs, false); in emac_hal_init_dma_default()
331 emac_ll_set_priority_ratio(hal->dma_regs, EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1); in emac_hal_init_dma_default()
334 void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write) in emac_hal_set_phy_cmd() argument
337 emac_ll_set_phy_addr(hal->mac_regs, phy_addr); in emac_hal_set_phy_cmd()
339 emac_ll_set_phy_reg(hal->mac_regs, phy_reg); in emac_hal_set_phy_cmd()
341 emac_ll_write_enable(hal->mac_regs, write); in emac_hal_set_phy_cmd()
343 emac_ll_set_busy(hal->mac_regs, true); in emac_hal_set_phy_cmd()
347 void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr) in emac_hal_set_address() argument
351 emac_ll_set_addr(hal->mac_regs, mac_addr); in emac_hal_set_address()
355 void emac_hal_start(emac_hal_context_t *hal) in emac_hal_start() argument
358 emac_ll_enable_corresponding_intr(hal->dma_regs, EMAC_LL_CONFIG_ENABLE_INTR_MASK); in emac_hal_start()
360 emac_ll_clear_all_pending_intr(hal->dma_regs); in emac_hal_start()
363 emac_ll_transmit_enable(hal->mac_regs, true); in emac_hal_start()
368 emac_ll_start_stop_dma_transmit(hal->dma_regs, true); in emac_hal_start()
371 emac_ll_start_stop_dma_receive(hal->dma_regs, true); in emac_hal_start()
373 emac_ll_receive_enable(hal->mac_regs, true); in emac_hal_start()
376 esp_err_t emac_hal_stop(emac_hal_context_t *hal) in emac_hal_stop() argument
379 emac_ll_start_stop_dma_transmit(hal->dma_regs, false); in emac_hal_stop()
381 if (emac_ll_transmit_frame_ctrl_status(hal->mac_regs) != 0x0) { in emac_hal_stop()
387 emac_ll_receive_enable(hal->mac_regs, false); in emac_hal_stop()
389 emac_ll_transmit_enable(hal->mac_regs, false); in emac_hal_stop()
391 if (emac_ll_receive_read_ctrl_state(hal->mac_regs) != 0x0) { in emac_hal_stop()
397 emac_ll_start_stop_dma_receive(hal->dma_regs, false); in emac_hal_stop()
400 emac_hal_flush_trans_fifo(hal); in emac_hal_stop()
403 emac_ll_disable_all_intr(hal->dma_regs); in emac_hal_stop()
408 uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length) in emac_hal_transmit_frame() argument
425 eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc; in emac_hal_transmit_frame()
463 hal->tx_desc->TDES0.Own = EMAC_LL_DMADESC_OWNER_DMA; in emac_hal_transmit_frame()
464 hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr); in emac_hal_transmit_frame()
466 emac_ll_transmit_poll_demand(hal->dma_regs, 0); in emac_hal_transmit_frame()
472 uint32_t emac_hal_transmit_multiple_buf_frame(emac_hal_context_t *hal, uint8_t **buffs, uint32_t *l… in emac_hal_transmit_multiple_buf_frame() argument
481 eth_dma_tx_descriptor_t *desc_iter = hal->tx_desc; in emac_hal_transmit_multiple_buf_frame()
551 hal->tx_desc->TDES0.Own = EMAC_LL_DMADESC_OWNER_DMA; in emac_hal_transmit_multiple_buf_frame()
552 hal->tx_desc = (eth_dma_tx_descriptor_t *)(hal->tx_desc->Buffer2NextDescAddr); in emac_hal_transmit_multiple_buf_frame()
554 emac_ll_transmit_poll_demand(hal->dma_regs, 0); in emac_hal_transmit_multiple_buf_frame()
560 uint8_t *emac_hal_alloc_recv_buf(emac_hal_context_t *hal, uint32_t *size) in emac_hal_alloc_recv_buf() argument
562 eth_dma_rx_descriptor_t *desc_iter = hal->rx_desc; in emac_hal_alloc_recv_buf()
599 uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *fra… in emac_hal_receive_frame() argument
601 eth_dma_rx_descriptor_t *desc_iter = hal->rx_desc; in emac_hal_receive_frame()
602 eth_dma_rx_descriptor_t *first_desc = hal->rx_desc; in emac_hal_receive_frame()
668 hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr); in emac_hal_receive_frame()
670 emac_ll_receive_poll_demand(hal->dma_regs, 0); in emac_hal_receive_frame()
678 uint32_t emac_hal_flush_recv_frame(emac_hal_context_t *hal, uint32_t *frames_remain, uint32_t *free… in emac_hal_flush_recv_frame() argument
680 eth_dma_rx_descriptor_t *desc_iter = hal->rx_desc; in emac_hal_flush_recv_frame()
681 eth_dma_rx_descriptor_t *first_desc = hal->rx_desc; in emac_hal_flush_recv_frame()
725 hal->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr); in emac_hal_flush_recv_frame()
727 emac_ll_receive_poll_demand(hal->dma_regs, 0); in emac_hal_flush_recv_frame()