28     emac_ll_flush_trans_fifo_enable(hal->dma_regs, true);  in emac_hal_flush_trans_fifo()
31         if (emac_ll_get_flush_trans_fifo(hal->dma_regs) == 0) {  in emac_hal_flush_trans_fifo()
149     hal->dma_regs = &EMAC_DMA;  in emac_hal_init()
217     emac_ll_set_rx_desc_addr(hal->dma_regs, (uint32_t)hal->rx_desc);  in emac_hal_reset_desc_chain()
218     emac_ll_set_tx_desc_addr(hal->dma_regs, (uint32_t)hal->tx_desc);  in emac_hal_reset_desc_chain()
295     emac_ll_drop_tcp_err_frame_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
297     emac_ll_recv_store_forward_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
299     emac_ll_flush_recv_frame_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
301     emac_ll_trans_store_forward_enable(hal->dma_regs, false);  in emac_hal_init_dma_default()
305     emac_ll_set_transmit_threshold(hal->dma_regs, EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_64);  in emac_hal_init_dma_default()
307     emac_ll_forward_err_frame_enable(hal->dma_regs, false);  in emac_hal_init_dma_default()
309     emac_ll_forward_undersized_good_frame_enable(hal->dma_regs, false);  in emac_hal_init_dma_default()
311     emac_ll_set_recv_threshold(hal->dma_regs, EMAC_LL_RECEIVE_THRESHOLD_CONTROL_64);  in emac_hal_init_dma_default()
313     emac_ll_opt_second_frame_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
317     emac_ll_mixed_burst_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
319     emac_ll_addr_align_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
321     emac_ll_use_separate_pbl_enable(hal->dma_regs, false);  in emac_hal_init_dma_default()
323     emac_ll_set_prog_burst_len(hal->dma_regs, hal_config->dma_burst_len);  in emac_hal_init_dma_default()
325     emac_ll_enhance_desc_enable(hal->dma_regs, true);  in emac_hal_init_dma_default()
327     emac_ll_set_desc_skip_len(hal->dma_regs, 0);  in emac_hal_init_dma_default()
329     emac_ll_fixed_arbitration_enable(hal->dma_regs, false);  in emac_hal_init_dma_default()
331     emac_ll_set_priority_ratio(hal->dma_regs, EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1);  in emac_hal_init_dma_default()
358     emac_ll_enable_corresponding_intr(hal->dma_regs, EMAC_LL_CONFIG_ENABLE_INTR_MASK);  in emac_hal_start()
360     emac_ll_clear_all_pending_intr(hal->dma_regs);  in emac_hal_start()
368     emac_ll_start_stop_dma_transmit(hal->dma_regs, true);  in emac_hal_start()
371     emac_ll_start_stop_dma_receive(hal->dma_regs, true);  in emac_hal_start()
379     emac_ll_start_stop_dma_transmit(hal->dma_regs, false);  in emac_hal_stop()
397     emac_ll_start_stop_dma_receive(hal->dma_regs, false);  in emac_hal_stop()
403     emac_ll_disable_all_intr(hal->dma_regs);  in emac_hal_stop()
466     emac_ll_transmit_poll_demand(hal->dma_regs, 0);  in emac_hal_transmit_frame()
554     emac_ll_transmit_poll_demand(hal->dma_regs, 0);  in emac_hal_transmit_multiple_buf_frame()
670         emac_ll_receive_poll_demand(hal->dma_regs, 0);  in emac_hal_receive_frame()
727         emac_ll_receive_poll_demand(hal->dma_regs, 0);  in emac_hal_flush_recv_frame()