42     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);  in emac_hal_iomux_init_mii()
45     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]);  in emac_hal_iomux_init_mii()
48     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]);  in emac_hal_iomux_init_mii()
51     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]);  in emac_hal_iomux_init_mii()
54     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[14]);  in emac_hal_iomux_init_mii()
57     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[12]);  in emac_hal_iomux_init_mii()
61     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[5]);  in emac_hal_iomux_init_mii()
64     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]);  in emac_hal_iomux_init_mii()
67     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]);  in emac_hal_iomux_init_mii()
70     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]);  in emac_hal_iomux_init_mii()
73     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[1]);  in emac_hal_iomux_init_mii()
76     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[15]);  in emac_hal_iomux_init_mii()
83     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);  in emac_hal_iomux_rmii_clk_input()
92         PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);  in emac_hal_iomux_rmii_clk_output()
97         PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);  in emac_hal_iomux_rmii_clk_output()
102         PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);  in emac_hal_iomux_rmii_clk_output()
113     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[21]);  in emac_hal_iomux_init_rmii()
116     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[19]);  in emac_hal_iomux_init_rmii()
119     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[22]);  in emac_hal_iomux_init_rmii()
123     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[27]);  in emac_hal_iomux_init_rmii()
126     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[25]);  in emac_hal_iomux_init_rmii()
129     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[26]);  in emac_hal_iomux_init_rmii()
136     PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[4]);  in emac_hal_iomux_init_tx_er()
143     PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[13]);  in emac_hal_iomux_init_rx_er()