Lines Matching refs:EFUSE_BLK0
19 {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses,
23 {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS,
27 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE,
31 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DCACHE,
35 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE,
39 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_DCACHE,
43 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD,
47 {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG,
51 {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI,
55 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_APP_CPU,
59 {EFUSE_BLK0, 2, 1}, // [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG,
63 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
67 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG,
71 {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG,
75 {EFUSE_BLK0, 2, 1}, // [] wr_dis of STRAP_JTAG_SEL,
79 {EFUSE_BLK0, 2, 1}, // [] wr_dis of USB_PHY_SEL,
83 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_XPD,
87 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH,
91 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_FORCE,
95 {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL,
99 {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT,
103 {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
107 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
111 {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
115 {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
119 {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
123 {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
127 {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
131 {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
135 {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
139 {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
143 {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
147 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW,
151 {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE,
155 {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT,
159 {EFUSE_BLK0, 18, 1}, // [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
163 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_MODE,
167 …{EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MO…
171 {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
175 {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL,
179 {EFUSE_BLK0, 18, 1}, // [] wr_dis of PIN_POWER_SELECTION,
183 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE,
187 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_PAGE_SIZE,
191 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN,
195 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME,
199 {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION,
203 {EFUSE_BLK0, 19, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE,
207 {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
211 {EFUSE_BLK0, 19, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
215 {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1,
219 {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
223 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK,
227 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q,
231 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D,
235 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS,
239 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_HD,
243 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_WP,
247 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_DQS,
251 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D4,
255 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D5,
259 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D6,
263 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D7,
267 {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_LO,
271 {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
275 {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR,
279 {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
283 {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP,
287 {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
291 {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
295 {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_TEMP,
299 {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR,
303 {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_RTC_LDO,
307 {EFUSE_BLK0, 20, 1}, // [] wr_dis of K_DIG_LDO,
311 {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_RTC_DBIAS20,
315 {EFUSE_BLK0, 20, 1}, // [] wr_dis of V_DIG_DBIAS20,
319 {EFUSE_BLK0, 20, 1}, // [] wr_dis of DIG_DBIAS_HVT,
323 {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_HI,
327 {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
331 {EFUSE_BLK0, 20, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN3,
335 {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
339 {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
343 {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
347 {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB,
351 {EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
355 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN0,
359 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN1,
363 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN2,
367 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_INIT_CODE_ATTEN3,
371 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN0,
375 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN1,
379 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN2,
383 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_INIT_CODE_ATTEN3,
387 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN0,
391 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN1,
395 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN2,
399 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CAL_VOL_ATTEN3,
403 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN0,
407 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN1,
411 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC2_CAL_VOL_ATTEN2,
415 {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
419 {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
423 {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
427 {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
431 {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
435 {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
439 {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
443 {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
447 {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
451 {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS,
455 {EFUSE_BLK0, 30, 1}, // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE,
459 {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG,
463 {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10,
467 {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
471 {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
475 {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
479 {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
483 {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
487 {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
491 {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
495 {EFUSE_BLK0, 40, 1}, // [] Set this bit to disable Icache,
499 {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable Dcache,
503 …{EFUSE_BLK0, 42, 1}, // [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0;…
507 …{EFUSE_BLK0, 43, 1}, // [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0…
511 …{EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download m…
515 {EFUSE_BLK0, 45, 1}, // [DIS_USB] Set this bit to disable USB function,
519 {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Set this bit to disable CAN function,
523 {EFUSE_BLK0, 47, 1}, // [] Disable app cpu,
527 …{EFUSE_BLK0, 48, 3}, // [] Set these bits to disable JTAG in the soft way (odd number 1 means di…
531 …{EFUSE_BLK0, 51, 1}, // [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is di…
535 … {EFUSE_BLK0, 52, 1}, // [] Set this bit to disable flash encryption when in download boot modes,
539 {EFUSE_BLK0, 57, 1}, // [] Set this bit to exchange USB D+ and D- pins,
543 {EFUSE_BLK0, 58, 1}, // [EXT_PHY_ENABLE] Set this bit to enable external PHY,
547 {EFUSE_BLK0, 68, 1}, // [] SPI regulator power up signal,
551 …{EFUSE_BLK0, 69, 1}, // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connec…
555 …{EFUSE_BLK0, 70, 1}, // [] Set this bit and force to use the configuration of eFuse to configure…
559 …{EFUSE_BLK0, 80, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "4000…
563 …{EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disabled otherw…
567 {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key,
571 {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key,
575 {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key,
579 {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of Key0,
583 {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of Key1,
587 {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of Key2,
591 {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of Key3,
595 {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of Key4,
599 {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of Key5,
603 {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot,
607 {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable revoking aggressive secure boot,
611 …{EFUSE_BLK0, 118, 1}, // [] Set this bit to disable function of usb switch to jtag in module of …
615 {EFUSE_BLK0, 119, 1}, // [DIS_USB_DEVICE] Set this bit to disable usb device,
619 …{EFUSE_BLK0, 120, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag…
623 …{EFUSE_BLK0, 121, 1}, // [] This bit is used to switch internal PHY and external PHY for USB OTG…
627 …{EFUSE_BLK0, 124, 4}, // [] Configures flash waiting time after power-up; in unit of ms. If the …
631 …{EFUSE_BLK0, 128, 1}, // [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; …
635 {EFUSE_BLK0, 129, 1}, // [DIS_LEGACY_SPI_BOOT] Disable direct boot mode,
639 {EFUSE_BLK0, 130, 1}, // [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"},
643 {EFUSE_BLK0, 131, 1}, // [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"},
647 …{EFUSE_BLK0, 132, 1}, // [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode thro…
651 {EFUSE_BLK0, 133, 1}, // [] Set this bit to enable secure UART download mode,
655 …{EFUSE_BLK0, 134, 2}, // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enab…
659 …{EFUSE_BLK0, 136, 1}, // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is in…
663 {EFUSE_BLK0, 137, 1}, // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"},
667 {EFUSE_BLK0, 138, 2}, // [] Set Flash page size,
671 {EFUSE_BLK0, 140, 1}, // [] Set 1 to enable ECC for flash boot,
675 …{EFUSE_BLK0, 141, 1}, // [] Set this bit to force ROM code to send a resume command during SPI b…
679 {EFUSE_BLK0, 142, 16}, // [] Secure version (used by ESP-IDF anti-rollback feature),
683 {EFUSE_BLK0, 159, 1}, // [] Set this bit to disable download through USB-OTG,
687 {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major,
691 {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major,