Lines Matching refs:EFUSE_BLK0

19     {EFUSE_BLK0, 0, 32}, 	 // [] Disable programming of individual eFuses,
23 {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS,
27 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE,
31 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DCACHE,
35 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_ICACHE,
39 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_DCACHE,
43 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD,
47 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB,
51 {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI,
55 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_BOOT_REMAP,
59 {EFUSE_BLK0, 2, 1}, // [] wr_dis of SOFT_DIS_JTAG,
63 {EFUSE_BLK0, 2, 1}, // [] wr_dis of HARD_DIS_JTAG,
67 {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
71 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_XPD,
75 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_TIEH,
79 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VDD_SPI_FORCE,
83 {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL,
87 {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT,
91 {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
95 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
99 {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
103 {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
107 {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
111 {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
115 {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
119 {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
123 {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
127 {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
131 {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
135 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW,
139 {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE,
143 {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_LEGACY_SPI_BOOT,
147 {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CHANNEL,
151 {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_DOWNLOAD_MODE,
155 {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
159 {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL,
163 {EFUSE_BLK0, 18, 1}, // [] wr_dis of PIN_POWER_SELECTION,
167 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE,
171 {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME,
175 {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION,
179 {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1,
183 {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
187 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK,
191 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q,
195 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D,
199 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS,
203 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_HD,
207 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_WP,
211 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_DQS,
215 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D4,
219 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D5,
223 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D6,
227 {EFUSE_BLK0, 20, 1}, // [] wr_dis of SPI_PAD_CONFIG_D7,
231 {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
235 {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_HI,
239 {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VERSION,
243 {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
247 {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VERSION,
251 {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
255 {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR_LO,
259 {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
263 {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
267 {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC_CALIB,
271 {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MINOR,
275 {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB,
279 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A10H,
283 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A11H,
287 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A12H,
291 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A13H,
295 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A20H,
299 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A21H,
303 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A22H,
307 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A23H,
311 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A10L,
315 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A11L,
319 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A12L,
323 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A13L,
327 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A20L,
331 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A21L,
335 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A22L,
339 {EFUSE_BLK0, 21, 1}, // [] wr_dis of RTCCALIB_V1IDX_A23L,
343 {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
347 {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
351 {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
355 {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
359 {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
363 {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
367 {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
371 {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
375 {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
379 {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS,
383 {EFUSE_BLK0, 30, 1}, // [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE,
387 {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_FORCE_NOPERSIST,
391 {EFUSE_BLK0, 30, 1}, // [] wr_dis of BLOCK0_VERSION,
395 {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10,
399 {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
403 {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
407 {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
411 {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
415 {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
419 {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
423 {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
427 {EFUSE_BLK0, 40, 1}, // [] Set this bit to disable Icache,
431 {EFUSE_BLK0, 41, 1}, // [] Set this bit to disable Dcache,
435 {EFUSE_BLK0, 42, 1}, // [] Disables Icache when SoC is in Download mode,
439 {EFUSE_BLK0, 43, 1}, // [] Disables Dcache when SoC is in Download mode,
443 …{EFUSE_BLK0, 44, 1}, // [] Set this bit to disable the function that forces chip into download m…
447 {EFUSE_BLK0, 45, 1}, // [] Set this bit to disable USB OTG function,
451 {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Set this bit to disable the TWAI Controller function,
455 {EFUSE_BLK0, 47, 1}, // [] Disables capability to Remap RAM to ROM address space,
459 …{EFUSE_BLK0, 49, 1}, // [] Software disables JTAG. When software disabled; JTAG can be activated…
463 {EFUSE_BLK0, 50, 1}, // [] Hardware disables JTAG permanently,
467 {EFUSE_BLK0, 51, 1}, // [] Disables flash encryption when in download boot modes,
471 {EFUSE_BLK0, 56, 1}, // [] Set this bit to exchange USB D+ and D- pins,
475 {EFUSE_BLK0, 57, 1}, // [EXT_PHY_ENABLE] Set this bit to enable external USB PHY,
479 {EFUSE_BLK0, 58, 1}, // [] If set; forces USB BVALID to 1,
483 {EFUSE_BLK0, 59, 2}, // [] BLOCK0 efuse version,
487 …{EFUSE_BLK0, 68, 1}, // [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator…
491 …{EFUSE_BLK0, 69, 1}, // [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connec…
495 …{EFUSE_BLK0, 70, 1}, // [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD…
499 …{EFUSE_BLK0, 80, 2}, // [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "4000…
503 …{EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disabled otherw…
507 {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key,
511 {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key,
515 {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key,
519 {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Purpose of KEY0,
523 {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Purpose of KEY1,
527 {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Purpose of KEY2,
531 {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Purpose of KEY3,
535 {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Purpose of KEY4,
539 {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Purpose of KEY5,
543 {EFUSE_BLK0, 116, 1}, // [] Set this bit to enable secure boot,
547 {EFUSE_BLK0, 117, 1}, // [] Set this bit to enable aggressive secure boot key revocation mode,
551 …{EFUSE_BLK0, 124, 4}, // [] Configures flash startup delay after SoC power-up; in unit of (ms/2)…
555 {EFUSE_BLK0, 128, 1}, // [] Set this bit to disable all download boot modes,
559 {EFUSE_BLK0, 129, 1}, // [] Set this bit to disable Legacy SPI boot mode,
563 …{EFUSE_BLK0, 130, 1}, // [] Selects the default UART for printing boot messages {0: "UART0"; 1: …
567 {EFUSE_BLK0, 132, 1}, // [] Set this bit to disable use of USB OTG in UART download boot mode,
571 …{EFUSE_BLK0, 133, 1}, // [] Set this bit to enable secure UART download mode (read/write flash o…
575 …{EFUSE_BLK0, 134, 2}, // [] Set the default UART boot message output mode {0: "Enable"; 1: "Enab…
579 …{EFUSE_BLK0, 136, 1}, // [] Set default power supply for GPIO33-GPIO37; set when SPI flash is in…
583 {EFUSE_BLK0, 137, 1}, // [] SPI flash type {0: "4 data lines"; 1: "8 data lines"},
587 …{EFUSE_BLK0, 138, 1}, // [] If set; forces ROM code to send an SPI flash resume command during S…
591 {EFUSE_BLK0, 139, 16}, // [] Secure version (used by ESP-IDF anti-rollback feature),
595 {EFUSE_BLK0, 160, 1}, // [] Disables check of wafer version major,
599 {EFUSE_BLK0, 161, 1}, // [] Disables check of blk version major,