Lines Matching refs:EFUSE_BLK0
30 {EFUSE_BLK0, 0, 16}, // [] Efuse write disable mask,
34 {EFUSE_BLK0, 0, 1}, // [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS,
38 {EFUSE_BLK0, 1, 1}, // [] wr_dis of WR_DIS,
42 {EFUSE_BLK0, 2, 1}, // [] wr_dis of FLASH_CRYPT_CNT,
46 {EFUSE_BLK0, 2, 1}, // [] wr_dis of UART_DOWNLOAD_DIS,
50 {EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
54 {EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC,
58 {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU,
62 {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT,
66 {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE,
70 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VOL_LEVEL_HP_INV,
74 {EFUSE_BLK0, 4, 1}, // [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ,
78 {EFUSE_BLK0, 4, 1}, // [] wr_dis of ADC_VREF,
82 {EFUSE_BLK0, 5, 1}, // [] wr_dis of XPD_SDIO_REG,
86 {EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH,
90 {EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE,
94 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK,
98 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q,
102 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_D,
106 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS0,
110 {EFUSE_BLK0, 7, 1}, // [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1,
114 {EFUSE_BLK0, 8, 1}, // [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2,
118 {EFUSE_BLK0, 9, 1}, // [WR_DIS.BLK3] wr_dis of BLOCK3,
122 {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC,
126 {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC,
130 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_LOW,
134 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_HIGH,
138 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_LOW,
142 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_HIGH,
146 {EFUSE_BLK0, 9, 1}, // [] wr_dis of SECURE_VERSION,
150 {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION,
154 {EFUSE_BLK0, 10, 1}, // [] wr_dis of BLK3_PART_RESERVE,
158 {EFUSE_BLK0, 10, 1}, // [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG,
162 {EFUSE_BLK0, 10, 1}, // [] wr_dis of CODING_SCHEME,
166 {EFUSE_BLK0, 10, 1}, // [] wr_dis of KEY_STATUS,
170 {EFUSE_BLK0, 12, 1}, // [] wr_dis of ABS_DONE_0,
174 {EFUSE_BLK0, 13, 1}, // [] wr_dis of ABS_DONE_1,
178 {EFUSE_BLK0, 14, 1}, // [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE,
182 {EFUSE_BLK0, 15, 1}, // [] wr_dis of CONSOLE_DEBUG_DISABLE,
186 {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_ENCRYPT,
190 {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_DECRYPT,
194 {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_CACHE,
198 {EFUSE_BLK0, 16, 4}, // [] Disable reading from BlOCK1-3,
202 {EFUSE_BLK0, 16, 1}, // [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1,
206 {EFUSE_BLK0, 17, 1}, // [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2,
210 {EFUSE_BLK0, 18, 1}, // [RD_DIS.BLK3] rd_dis of BLOCK3,
214 {EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC,
218 {EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC,
222 {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC1_TP_LOW,
226 {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC1_TP_HIGH,
230 {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC2_TP_LOW,
234 {EFUSE_BLK0, 18, 1}, // [] rd_dis of ADC2_TP_HIGH,
238 {EFUSE_BLK0, 18, 1}, // [] rd_dis of SECURE_VERSION,
242 {EFUSE_BLK0, 18, 1}, // [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION,
246 {EFUSE_BLK0, 19, 1}, // [] rd_dis of BLK3_PART_RESERVE,
250 {EFUSE_BLK0, 19, 1}, // [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG,
254 {EFUSE_BLK0, 19, 1}, // [] rd_dis of CODING_SCHEME,
258 {EFUSE_BLK0, 19, 1}, // [] rd_dis of KEY_STATUS,
262 …{EFUSE_BLK0, 20, 7}, // [] Flash encryption is enabled if this field has an odd number of bits s…
266 {EFUSE_BLK0, 27, 1}, // [] Disable UART download mode. Valid for ESP32 V3 and newer; only,
270 {EFUSE_BLK0, 72, 8}, // [MAC_FACTORY] MAC address,
271 {EFUSE_BLK0, 64, 8}, // [MAC_FACTORY] MAC address,
272 {EFUSE_BLK0, 56, 8}, // [MAC_FACTORY] MAC address,
273 {EFUSE_BLK0, 48, 8}, // [MAC_FACTORY] MAC address,
274 {EFUSE_BLK0, 40, 8}, // [MAC_FACTORY] MAC address,
275 {EFUSE_BLK0, 32, 8}, // [MAC_FACTORY] MAC address,
279 {EFUSE_BLK0, 80, 8}, // [MAC_FACTORY_CRC] CRC8 for MAC address,
283 {EFUSE_BLK0, 96, 1}, // [CHIP_VER_DIS_APP_CPU] Disables APP CPU,
287 {EFUSE_BLK0, 97, 1}, // [CHIP_VER_DIS_BT] Disables Bluetooth,
291 {EFUSE_BLK0, 98, 1}, // [CHIP_VER_PKG_4BIT] Chip package identifier #4bit,
295 {EFUSE_BLK0, 99, 1}, // [CHIP_VER_DIS_CACHE] Disables cache,
299 {EFUSE_BLK0, 100, 5}, // [] read for SPI_pad_config_hd,
303 {EFUSE_BLK0, 105, 3}, // [CHIP_VER_PKG] Chip package identifier,
307 …{EFUSE_BLK0, 108, 1}, // [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32's max CPU f…
311 {EFUSE_BLK0, 109, 1}, // [] If set; the ESP32's maximum CPU frequency has been rated,
315 {EFUSE_BLK0, 110, 1}, // [] BLOCK3 partially served for ADC calibration data,
319 {EFUSE_BLK0, 111, 1}, // [] bit is set to 1 for rev1 silicon,
323 {EFUSE_BLK0, 128, 8}, // [CK8M_FREQ] 8MHz clock freq override,
327 {EFUSE_BLK0, 136, 5}, // [] True ADC reference voltage,
331 {EFUSE_BLK0, 142, 1}, // [] read for XPD_SDIO_REG,
335 {EFUSE_BLK0, 143, 1}, // [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: "3.3V"; 0: "1.8V"},
339 {EFUSE_BLK0, 144, 1}, // [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset,
343 {EFUSE_BLK0, 160, 5}, // [] Override SD_CLK pad (GPIO6/SPICLK),
347 {EFUSE_BLK0, 165, 5}, // [] Override SD_DATA_0 pad (GPIO7/SPIQ),
351 {EFUSE_BLK0, 170, 5}, // [] Override SD_DATA_1 pad (GPIO8/SPID),
355 {EFUSE_BLK0, 175, 5}, // [] Override SD_CMD pad (GPIO11/SPICS0),
359 {EFUSE_BLK0, 180, 1}, // [],
363 …{EFUSE_BLK0, 182, 2}, // [] This field stores the voltage level for CPU to run at 240 MHz; or fo…
367 {EFUSE_BLK0, 184, 2}, // [],
371 {EFUSE_BLK0, 188, 4}, // [ENCRYPT_CONFIG] Flash encryption config (key tweak bits),
375 …{EFUSE_BLK0, 192, 2}, // [] Efuse variable block length scheme {0: "NONE (BLK1-3 len=256 bits)";…
379 {EFUSE_BLK0, 194, 1}, // [] Disable ROM BASIC interpreter fallback,
383 {EFUSE_BLK0, 195, 1}, // [],
387 {EFUSE_BLK0, 196, 1}, // [] Secure boot V1 is enabled for bootloader image,
391 {EFUSE_BLK0, 197, 1}, // [] Secure boot V2 is enabled for bootloader image,
395 {EFUSE_BLK0, 198, 1}, // [DISABLE_JTAG] Disable JTAG,
399 {EFUSE_BLK0, 199, 1}, // [] Disable flash encryption in UART bootloader,
403 {EFUSE_BLK0, 200, 1}, // [] Disable flash decryption in UART bootloader,
407 {EFUSE_BLK0, 201, 1}, // [] Disable flash cache in UART bootloader,
411 {EFUSE_BLK0, 202, 1}, // [] Usage of efuse block 3 (reserved),