Lines Matching full:wr_dis
29 static const esp_efuse_desc_t WR_DIS[] = { variable
34 {EFUSE_BLK0, 0, 1}, // [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS,
38 {EFUSE_BLK0, 1, 1}, // [] wr_dis of WR_DIS,
42 {EFUSE_BLK0, 2, 1}, // [] wr_dis of FLASH_CRYPT_CNT,
46 {EFUSE_BLK0, 2, 1}, // [] wr_dis of UART_DOWNLOAD_DIS,
50 {EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
54 {EFUSE_BLK0, 3, 1}, // [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC,
58 {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU,
62 {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT,
66 {EFUSE_BLK0, 3, 1}, // [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE,
70 {EFUSE_BLK0, 3, 1}, // [] wr_dis of VOL_LEVEL_HP_INV,
74 {EFUSE_BLK0, 4, 1}, // [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ,
78 {EFUSE_BLK0, 4, 1}, // [] wr_dis of ADC_VREF,
82 {EFUSE_BLK0, 5, 1}, // [] wr_dis of XPD_SDIO_REG,
86 {EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH,
90 {EFUSE_BLK0, 5, 1}, // [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE,
94 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CLK,
98 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_Q,
102 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_D,
106 {EFUSE_BLK0, 6, 1}, // [] wr_dis of SPI_PAD_CONFIG_CS0,
110 {EFUSE_BLK0, 7, 1}, // [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1,
114 {EFUSE_BLK0, 8, 1}, // [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2,
118 {EFUSE_BLK0, 9, 1}, // [WR_DIS.BLK3] wr_dis of BLOCK3,
122 {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC,
126 {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC,
130 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_LOW,
134 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC1_TP_HIGH,
138 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_LOW,
142 {EFUSE_BLK0, 9, 1}, // [] wr_dis of ADC2_TP_HIGH,
146 {EFUSE_BLK0, 9, 1}, // [] wr_dis of SECURE_VERSION,
150 {EFUSE_BLK0, 9, 1}, // [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION,
154 {EFUSE_BLK0, 10, 1}, // [] wr_dis of BLK3_PART_RESERVE,
158 {EFUSE_BLK0, 10, 1}, // [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG,
162 {EFUSE_BLK0, 10, 1}, // [] wr_dis of CODING_SCHEME,
166 {EFUSE_BLK0, 10, 1}, // [] wr_dis of KEY_STATUS,
170 {EFUSE_BLK0, 12, 1}, // [] wr_dis of ABS_DONE_0,
174 {EFUSE_BLK0, 13, 1}, // [] wr_dis of ABS_DONE_1,
178 {EFUSE_BLK0, 14, 1}, // [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE,
182 {EFUSE_BLK0, 15, 1}, // [] wr_dis of CONSOLE_DEBUG_DISABLE,
186 {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_ENCRYPT,
190 {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_DECRYPT,
194 {EFUSE_BLK0, 15, 1}, // [] wr_dis of DISABLE_DL_CACHE,
459 &WR_DIS[0], // [] Efuse write disable mask
464 &WR_DIS_RD_DIS[0], // [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS
469 &WR_DIS_WR_DIS[0], // [] wr_dis of WR_DIS
474 &WR_DIS_FLASH_CRYPT_CNT[0], // [] wr_dis of FLASH_CRYPT_CNT
479 &WR_DIS_UART_DOWNLOAD_DIS[0], // [] wr_dis of UART_DOWNLOAD_DIS
484 &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC
489 &WR_DIS_MAC_CRC[0], // [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC
494 &WR_DIS_DISABLE_APP_CPU[0], // [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU
499 &WR_DIS_DISABLE_BT[0], // [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT
504 &WR_DIS_DIS_CACHE[0], // [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE
509 &WR_DIS_VOL_LEVEL_HP_INV[0], // [] wr_dis of VOL_LEVEL_HP_INV
514 &WR_DIS_CLK8M_FREQ[0], // [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ
519 &WR_DIS_ADC_VREF[0], // [] wr_dis of ADC_VREF
524 &WR_DIS_XPD_SDIO_REG[0], // [] wr_dis of XPD_SDIO_REG
529 &WR_DIS_XPD_SDIO_TIEH[0], // [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH
534 &WR_DIS_XPD_SDIO_FORCE[0], // [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE
539 &WR_DIS_SPI_PAD_CONFIG_CLK[0], // [] wr_dis of SPI_PAD_CONFIG_CLK
544 &WR_DIS_SPI_PAD_CONFIG_Q[0], // [] wr_dis of SPI_PAD_CONFIG_Q
549 &WR_DIS_SPI_PAD_CONFIG_D[0], // [] wr_dis of SPI_PAD_CONFIG_D
554 &WR_DIS_SPI_PAD_CONFIG_CS0[0], // [] wr_dis of SPI_PAD_CONFIG_CS0
559 &WR_DIS_BLOCK1[0], // [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1
564 &WR_DIS_BLOCK2[0], // [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2
569 &WR_DIS_BLOCK3[0], // [WR_DIS.BLK3] wr_dis of BLOCK3
574 &WR_DIS_CUSTOM_MAC_CRC[0], // [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC
579 &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC
584 &WR_DIS_ADC1_TP_LOW[0], // [] wr_dis of ADC1_TP_LOW
589 &WR_DIS_ADC1_TP_HIGH[0], // [] wr_dis of ADC1_TP_HIGH
594 &WR_DIS_ADC2_TP_LOW[0], // [] wr_dis of ADC2_TP_LOW
599 &WR_DIS_ADC2_TP_HIGH[0], // [] wr_dis of ADC2_TP_HIGH
604 &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION
609 &WR_DIS_MAC_VERSION[0], // [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION
614 &WR_DIS_BLK3_PART_RESERVE[0], // [] wr_dis of BLK3_PART_RESERVE
619 &WR_DIS_FLASH_CRYPT_CONFIG[0], // [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG
624 &WR_DIS_CODING_SCHEME[0], // [] wr_dis of CODING_SCHEME
629 &WR_DIS_KEY_STATUS[0], // [] wr_dis of KEY_STATUS
634 &WR_DIS_ABS_DONE_0[0], // [] wr_dis of ABS_DONE_0
639 &WR_DIS_ABS_DONE_1[0], // [] wr_dis of ABS_DONE_1
644 &WR_DIS_JTAG_DISABLE[0], // [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE
649 &WR_DIS_CONSOLE_DEBUG_DISABLE[0], // [] wr_dis of CONSOLE_DEBUG_DISABLE
654 &WR_DIS_DISABLE_DL_ENCRYPT[0], // [] wr_dis of DISABLE_DL_ENCRYPT
659 &WR_DIS_DISABLE_DL_DECRYPT[0], // [] wr_dis of DISABLE_DL_DECRYPT
664 &WR_DIS_DISABLE_DL_CACHE[0], // [] wr_dis of DISABLE_DL_CACHE