Lines Matching refs:uart_context
160 static uart_context_t uart_context[UART_NUM_MAX] = { variable
172 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_module_enable()
173 if (uart_context[uart_num].hw_enabled != true) { in uart_module_enable()
179 uart_hal_set_reset_core(&(uart_context[uart_num].hal), true); in uart_module_enable()
181 uart_hal_set_reset_core(&(uart_context[uart_num].hal), false); in uart_module_enable()
186 uart_context[uart_num].hw_enabled = true; in uart_module_enable()
188 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_module_enable()
193 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_module_disable()
194 if (uart_context[uart_num].hw_enabled != false) { in uart_module_disable()
198 uart_context[uart_num].hw_enabled = false; in uart_module_disable()
200 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_module_disable()
212 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_word_length()
213 uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), data_bit); in uart_set_word_length()
214 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_word_length()
221 uart_hal_get_data_bit_num(&(uart_context[uart_num].hal), data_bit); in uart_get_word_length()
229 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_stop_bits()
230 uart_hal_set_stop_bits(&(uart_context[uart_num].hal), stop_bit); in uart_set_stop_bits()
231 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_stop_bits()
238 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_stop_bits()
239 uart_hal_get_stop_bits(&(uart_context[uart_num].hal), stop_bit); in uart_get_stop_bits()
240 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_stop_bits()
247 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_parity()
248 uart_hal_set_parity(&(uart_context[uart_num].hal), parity_mode); in uart_set_parity()
249 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_parity()
256 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_parity()
257 uart_hal_get_parity(&(uart_context[uart_num].hal), parity_mode); in uart_get_parity()
258 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_parity()
269 uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk); in uart_set_baudrate()
272 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_baudrate()
273 uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq); in uart_set_baudrate()
274 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_baudrate()
285 uart_hal_get_sclk(&(uart_context[uart_num].hal), &src_clk); in uart_get_baudrate()
288 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_baudrate()
289 uart_hal_get_baudrate(&(uart_context[uart_num].hal), baudrate, sclk_freq); in uart_get_baudrate()
290 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_baudrate()
297 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_line_inverse()
298 uart_hal_inverse_signal(&(uart_context[uart_num].hal), inverse_mask); in uart_set_line_inverse()
299 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_line_inverse()
314 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_sw_flow_ctrl()
315 uart_hal_set_sw_flow_ctrl(&(uart_context[uart_num].hal), &sw_flow_ctl, enable); in uart_set_sw_flow_ctrl()
316 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_sw_flow_ctrl()
325 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_hw_flow_ctrl()
326 uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl, rx_thresh); in uart_set_hw_flow_ctrl()
327 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_hw_flow_ctrl()
334 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_hw_flow_ctrl()
335 uart_hal_get_hw_flow_ctrl(&(uart_context[uart_num].hal), flow_ctrl); in uart_get_hw_flow_ctrl()
336 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_hw_flow_ctrl()
343 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), clr_mask); in uart_clear_intr_status()
350 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_enable_intr_mask()
357 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), enable_mask); in uart_enable_intr_mask()
358 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), enable_mask); in uart_enable_intr_mask()
359 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_enable_intr_mask()
375 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_reenable_intr_mask()
379 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), mask); in uart_reenable_intr_mask()
380 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), mask); in uart_reenable_intr_mask()
381 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_reenable_intr_mask()
388 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_disable_intr_mask()
390 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), disable_mask); in uart_disable_intr_mask()
391 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_disable_intr_mask()
398 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_link_free()
405 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_link_free()
471 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_pop_pos()
478 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_pop_pos()
485 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_get_pos()
491 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_get_pos()
504 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_queue_reset()
510 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_pattern_queue_reset()
541 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET); in uart_enable_pattern_det_baud_intr()
542 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_enable_pattern_det_baud_intr()
543 uart_hal_set_at_cmd_char(&(uart_context[uart_num].hal), &at_cmd); in uart_enable_pattern_det_baud_intr()
544 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET); in uart_enable_pattern_det_baud_intr()
545 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_enable_pattern_det_baud_intr()
574 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_enable_tx_intr()
575 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_enable_tx_intr()
576 uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), thresh); in uart_enable_tx_intr()
577 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_enable_tx_intr()
578 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_enable_tx_intr()
650 …ESP_RETURN_ON_FALSE((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))), ESP_FAIL, UART_TAG, "… in uart_set_rts()
651 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_rts()
652 uart_hal_set_rts(&(uart_context[uart_num].hal), level); in uart_set_rts()
653 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_rts()
660 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_dtr()
661 uart_hal_set_dtr(&(uart_context[uart_num].hal), level); in uart_set_dtr()
662 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_dtr()
670 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_tx_idle_num()
671 uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), idle_num); in uart_set_tx_idle_num()
672 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_tx_idle_num()
693 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_param_config()
694 uart_hal_init(&(uart_context[uart_num].hal), uart_num); in uart_param_config()
695 uart_hal_set_sclk(&(uart_context[uart_num].hal), clk_src); in uart_param_config()
696 uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); in uart_param_config()
697 uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity); in uart_param_config()
698 uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits); in uart_param_config()
699 uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits); in uart_param_config()
700 uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), UART_TX_IDLE_NUM_DEFAULT); in uart_param_config()
701 …uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), uart_config->flow_ctrl, uart_config->rx_f… in uart_param_config()
702 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_param_config()
703 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); in uart_param_config()
704 uart_hal_txfifo_rst(&(uart_context[uart_num].hal)); in uart_param_config()
712 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); in uart_intr_config()
713 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_intr_config()
715 uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), intr_conf->rx_timeout_thresh); in uart_intr_config()
718 uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), 0); in uart_intr_config()
721 uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), intr_conf->rxfifo_full_thresh); in uart_intr_config()
724 … uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), intr_conf->txfifo_empty_intr_thresh); in uart_intr_config()
726 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), intr_conf->intr_enable_mask); in uart_intr_config()
727 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_intr_config()
752 UART_ENTER_CRITICAL_SAFE(&(uart_context[uart_num].spinlock)); in uart_enable_tx_write_fifo()
754 uart_hal_set_rts(&(uart_context[uart_num].hal), 0); in uart_enable_tx_write_fifo()
757 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); in uart_enable_tx_write_fifo()
758 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); in uart_enable_tx_write_fifo()
760 uart_hal_write_txfifo(&(uart_context[uart_num].hal), pbuf, len, &sent_len); in uart_enable_tx_write_fifo()
761 UART_EXIT_CRITICAL_SAFE(&(uart_context[uart_num].spinlock)); in uart_enable_tx_write_fifo()
778 uart_intr_status = uart_hal_get_intsts_mask(&(uart_context[uart_num].hal)); in uart_rx_intr_handler_default()
785 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
786 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_rx_intr_handler_default()
787 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
788 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_rx_intr_handler_default()
802 uint32_t tx_fifo_rem = uart_hal_get_txfifo_len(&(uart_context[uart_num].hal)); in uart_rx_intr_handler_default()
849 … uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); in uart_rx_intr_handler_default()
850 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
851 … uart_hal_tx_break(&(uart_context[uart_num].hal), p_uart->tx_brk_len); in uart_rx_intr_handler_default()
852 … uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); in uart_rx_intr_handler_default()
853 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
868 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_rx_intr_handler_default()
869 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
870 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_rx_intr_handler_default()
871 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
883 rx_fifo_len = uart_hal_get_rxfifo_len(&(uart_context[uart_num].hal)); in uart_rx_intr_handler_default()
887 … uart_hal_read_rxfifo(&(uart_context[uart_num].hal), p_uart->rx_data_buf, &rx_fifo_len); in uart_rx_intr_handler_default()
891 uart_hal_get_at_cmd_char(&(uart_context[uart_num].hal), &pat_chr, &pat_num); in uart_rx_intr_handler_default()
895 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET); in uart_rx_intr_handler_default()
901 …uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO_F… in uart_rx_intr_handler_default()
916 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
917 …uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT | UART_INTR_RXFIFO… in uart_rx_intr_handler_default()
918 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
920 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
932 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
941 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
952 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
955 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
956 …uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO… in uart_rx_intr_handler_default()
957 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
958 …uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO_T… in uart_rx_intr_handler_default()
960 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET); in uart_rx_intr_handler_default()
968 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
969 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); in uart_rx_intr_handler_default()
970 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
976 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_OVF); in uart_rx_intr_handler_default()
979 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_BRK_DET); in uart_rx_intr_handler_default()
987 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_FRAM_ERR); in uart_rx_intr_handler_default()
995 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_PARITY_ERR); in uart_rx_intr_handler_default()
998 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
999 uart_hal_tx_break(&(uart_context[uart_num].hal), 0); in uart_rx_intr_handler_default()
1000 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); in uart_rx_intr_handler_default()
1002 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TXFIFO_EMPTY); in uart_rx_intr_handler_default()
1004 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1005 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); in uart_rx_intr_handler_default()
1013 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1014 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE); in uart_rx_intr_handler_default()
1015 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1016 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_IDLE); in uart_rx_intr_handler_default()
1018 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_CMD_CHAR_DET); in uart_rx_intr_handler_default()
1024 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1025 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); in uart_rx_intr_handler_default()
1028 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1029 …uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_RS485_CLASH | UART_INTR_RS485_FR… in uart_rx_intr_handler_default()
1032 …E_SET(uart_num, UART_MODE_RS485_HALF_DUPLEX) && uart_hal_is_tx_idle(&(uart_context[uart_num].hal))… in uart_rx_intr_handler_default()
1040 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); in uart_rx_intr_handler_default()
1041 UART_ENTER_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1042 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); in uart_rx_intr_handler_default()
1044 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); in uart_rx_intr_handler_default()
1045 uart_hal_set_rts(&(uart_context[uart_num].hal), 1); in uart_rx_intr_handler_default()
1047 UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock)); in uart_rx_intr_handler_default()
1053 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_WAKEUP); in uart_rx_intr_handler_default()
1058 …uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), uart_intr_status); /*simply clear all othe… in uart_rx_intr_handler_default()
1090 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_wait_tx_done()
1092 …bool disabled = !(uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_TX_DONE); in uart_wait_tx_done()
1097 uart_hal_get_intraw_mask(&(uart_context[uart_num].hal)) & UART_INTR_TX_DONE)); in uart_wait_tx_done()
1101 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); in uart_wait_tx_done()
1103 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_wait_tx_done()
1110 if (uart_hal_is_tx_idle(&(uart_context[uart_num].hal))) { in uart_wait_tx_done()
1114 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_wait_tx_done()
1115 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_DONE); in uart_wait_tx_done()
1116 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_wait_tx_done()
1193 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); in uart_tx_all()
1194 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_tx_all()
1195 uart_hal_tx_break(&(uart_context[uart_num].hal), brk_len); in uart_tx_all()
1196 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_TX_BRK_DONE); in uart_tx_all()
1197 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_tx_all()
1229 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_check_buf_full()
1232 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_check_buf_full()
1281 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_read_bytes()
1285 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_read_bytes()
1305 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_buffered_data_len()
1307 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_get_buffered_data_len()
1332 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1333 …uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_FULL | UART_INTR_RXFIFO… in uart_flush_input()
1334 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1338 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1341 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1349 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1356 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1363 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1366 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1371 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1374 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_flush_input()
1381 uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); in uart_flush_input()
1585 uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); in uart_driver_install()
1586 uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK); in uart_driver_install()
1620 uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk); in uart_driver_delete()
1653 …ESP_RETURN_ON_FALSE((!uart_hal_is_hw_rts_en(&(uart_context[uart_num].hal))), ESP_ERR_INVALID_ARG, … in uart_set_mode()
1656 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_mode()
1657 uart_hal_set_mode(&(uart_context[uart_num].hal), mode); in uart_set_mode()
1662 uart_hal_ena_intr_mask(&(uart_context[uart_num].hal), UART_INTR_RXFIFO_TOUT in uart_set_mode()
1669 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_mode()
1682 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_rx_full_threshold()
1683 if (uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_RXFIFO_FULL) { in uart_set_rx_full_threshold()
1684 uart_hal_set_rxfifo_full_thr(&(uart_context[uart_num].hal), threshold); in uart_set_rx_full_threshold()
1686 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_rx_full_threshold()
1699 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_tx_empty_threshold()
1700 if (uart_hal_get_intr_ena_status(&(uart_context[uart_num].hal)) & UART_INTR_TXFIFO_EMPTY) { in uart_set_tx_empty_threshold()
1701 uart_hal_set_txfifo_empty_thr(&(uart_context[uart_num].hal), threshold); in uart_set_tx_empty_threshold()
1703 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_tx_empty_threshold()
1711 uint16_t tout_max_thresh = uart_hal_get_max_rx_timeout_thrd(&(uart_context[uart_num].hal)); in uart_set_rx_timeout()
1716 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_rx_timeout()
1717 uart_hal_set_rx_timeout(&(uart_context[uart_num].hal), tout_thresh); in uart_set_rx_timeout()
1718 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_rx_timeout()
1738 UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_wakeup_threshold()
1739 uart_hal_set_wakeup_thrd(&(uart_context[uart_num].hal), wakeup_threshold); in uart_set_wakeup_threshold()
1740 UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); in uart_set_wakeup_threshold()
1748 uart_hal_get_wakeup_thrd(&(uart_context[uart_num].hal), (uint32_t *)out_wakeup_threshold); in uart_get_wakeup_threshold()
1755 while (!uart_hal_is_tx_idle(&(uart_context[uart_num].hal))); in uart_wait_tx_idle_polling()
1762 uart_hal_set_loop_back(&(uart_context[uart_num].hal), loop_back_en); in uart_set_loop_back()
1768 uint16_t rx_tout = uart_hal_get_rx_tout_thr(&(uart_context[uart_num].hal)); in uart_set_always_rx_timeout()