41 static dedic_gpio_platform_t *s_platform[SOC_CPU_CORES_NUM];  variable
73     if (!s_platform[core_id]) {  in dedic_gpio_build_platform()
76         if (!s_platform[core_id]) {  in dedic_gpio_build_platform()
77             s_platform[core_id] = calloc(1, sizeof(dedic_gpio_platform_t));  in dedic_gpio_build_platform()
78             if (s_platform[core_id]) {  in dedic_gpio_build_platform()
80                 s_platform[core_id]->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;  in dedic_gpio_build_platform()
82 …s_platform[core_id]->out_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1…  in dedic_gpio_build_platform()
83 … s_platform[core_id]->in_occupied_mask = UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);  in dedic_gpio_build_platform()
85                 s_platform[core_id]->dev = &DEDIC_GPIO;  in dedic_gpio_build_platform()
94 …ESP_GOTO_ON_FALSE(s_platform[core_id], ESP_ERR_NO_MEM, err, TAG, "no mem for s_platform[%d]", core…  in dedic_gpio_build_platform()
95         ESP_LOGD(TAG, "build platform on core[%d] at %p", core_id, s_platform);  in dedic_gpio_build_platform()
104     if (s_platform[core_id]) {  in dedic_gpio_break_platform()
107         if (s_platform[core_id]) {  in dedic_gpio_break_platform()
108             free(s_platform[core_id]);  in dedic_gpio_break_platform()
109             s_platform[core_id] = NULL;  in dedic_gpio_break_platform()
149     if (!s_platform[core_id]->intr_hdl) {  in dedic_gpio_install_interrupt()
152         if (!s_platform[core_id]->intr_hdl) {  in dedic_gpio_install_interrupt()
154 …gpio_periph_signals.irq, isr_flags, dedic_gpio_default_isr, s_platform[core_id], &s_platform[core_…  in dedic_gpio_install_interrupt()
156             uint32_t status = dedic_gpio_ll_get_interrupt_status(s_platform[core_id]->dev);  in dedic_gpio_install_interrupt()
157             dedic_gpio_ll_clear_interrupt_status(s_platform[core_id]->dev, status);  in dedic_gpio_install_interrupt()
169     if (s_platform[core_id]->intr_hdl) {  in dedic_gpio_uninstall_interrupt()
172         if (s_platform[core_id]->intr_hdl) {  in dedic_gpio_uninstall_interrupt()
173             esp_intr_free(s_platform[core_id]->intr_hdl);  in dedic_gpio_uninstall_interrupt()
174             s_platform[core_id]->intr_hdl = NULL;  in dedic_gpio_uninstall_interrupt()
176             dedic_gpio_ll_enable_interrupt(s_platform[core_id]->dev, ~0UL, false);  in dedic_gpio_uninstall_interrupt()
184     dedic_gpio_ll_set_interrupt_type(s_platform[core_id]->dev, channel, type);  in dedic_gpio_set_interrupt()
186         dedic_gpio_ll_enable_interrupt(s_platform[core_id]->dev, 1 << channel, true);  in dedic_gpio_set_interrupt()
188         dedic_gpio_ll_enable_interrupt(s_platform[core_id]->dev, 1 << channel, false);  in dedic_gpio_set_interrupt()
219         portENTER_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_new_bundle()
221             if ((s_platform[core_id]->out_occupied_mask & (pattern << i)) == 0) {  in dedic_gpio_new_bundle()
228             s_platform[core_id]->out_occupied_mask |= out_mask;  in dedic_gpio_new_bundle()
231             dedic_gpio_ll_enable_instruction_access_out(s_platform[core_id]->dev, out_mask, true);  in dedic_gpio_new_bundle()
234         portEXIT_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_new_bundle()
245         portENTER_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_new_bundle()
247             if ((s_platform[core_id]->in_occupied_mask & (pattern << i)) == 0) {  in dedic_gpio_new_bundle()
254             s_platform[core_id]->in_occupied_mask |= in_mask;  in dedic_gpio_new_bundle()
256         portEXIT_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_new_bundle()
274         dedic_gpio_cpu_ll_enable_output(s_platform[core_id]->out_occupied_mask);  in dedic_gpio_new_bundle()
291     if (s_platform[core_id] && (out_mask || in_mask)) {  in dedic_gpio_new_bundle()
292         portENTER_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_new_bundle()
293         s_platform[core_id]->out_occupied_mask &= ~out_mask;  in dedic_gpio_new_bundle()
294         s_platform[core_id]->in_occupied_mask &= ~in_mask;  in dedic_gpio_new_bundle()
295         portEXIT_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_new_bundle()
312     portENTER_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_del_bundle()
313     s_platform[core_id]->out_occupied_mask &= ~(bundle->out_mask);  in dedic_gpio_del_bundle()
314     s_platform[core_id]->in_occupied_mask &= ~(bundle->in_mask);  in dedic_gpio_del_bundle()
315 …if (s_platform[core_id]->in_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM)…  in dedic_gpio_del_bundle()
316 …s_platform[core_id]->out_occupied_mask == (UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) -…  in dedic_gpio_del_bundle()
319     portEXIT_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_del_bundle()
407         portENTER_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_bundle_set_interrupt_and_callback()
409         portEXIT_CRITICAL(&s_platform[core_id]->spinlock);  in dedic_gpio_bundle_set_interrupt_and_callback()
411         s_platform[core_id]->cbs[channel] = cb_isr;  in dedic_gpio_bundle_set_interrupt_and_callback()
412         s_platform[core_id]->cb_args[channel] = cb_args;  in dedic_gpio_bundle_set_interrupt_and_callback()
413         s_platform[core_id]->in_bundles[channel] = bundle;  in dedic_gpio_bundle_set_interrupt_and_callback()