Lines Matching refs:p_i2s
141 static i2s_obj_t *p_i2s[SOC_I2S_NUM] = { variable
161 i2s_obj_t *p_i2s = (i2s_obj_t *) user_data; in i2s_dma_rx_callback() local
168 if (p_i2s->rx) { in i2s_dma_rx_callback()
171 if (xQueueIsQueueFullFromISR(p_i2s->rx->queue)) { in i2s_dma_rx_callback()
172 xQueueReceiveFromISR(p_i2s->rx->queue, &dummy, &tmp); in i2s_dma_rx_callback()
174 if (p_i2s->i2s_queue) { in i2s_dma_rx_callback()
176 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_dma_rx_callback()
180 xQueueSendFromISR(p_i2s->rx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp); in i2s_dma_rx_callback()
182 if (p_i2s->i2s_queue) { in i2s_dma_rx_callback()
184 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_dma_rx_callback()
193 i2s_obj_t *p_i2s = (i2s_obj_t *) user_data; in i2s_dma_tx_callback() local
199 if (p_i2s->tx) { in i2s_dma_tx_callback()
202 if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) { in i2s_dma_tx_callback()
203 xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &tmp); in i2s_dma_tx_callback()
205 if (p_i2s->i2s_queue) { in i2s_dma_tx_callback()
207 i2s_event.size = p_i2s->tx->buf_size; in i2s_dma_tx_callback()
208 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_dma_tx_callback()
212 if (p_i2s->tx_desc_auto_clear) { in i2s_dma_tx_callback()
213 memset((void *) (((lldesc_t *)finish_desc)->buf), 0, p_i2s->tx->buf_size); in i2s_dma_tx_callback()
215 xQueueSendFromISR(p_i2s->tx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp); in i2s_dma_tx_callback()
217 if (p_i2s->i2s_queue) { in i2s_dma_tx_callback()
219 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_dma_tx_callback()
229 i2s_obj_t *p_i2s = (i2s_obj_t *) arg; in i2s_intr_handler_default() local
230 uint32_t status = i2s_hal_get_intr_status(&(p_i2s->hal)); in i2s_intr_handler_default()
243 if (p_i2s->i2s_queue) { in i2s_intr_handler_default()
245 if (xQueueIsQueueFullFromISR(p_i2s->i2s_queue)) { in i2s_intr_handler_default()
246 xQueueReceiveFromISR(p_i2s->i2s_queue, &dummy, &tmp); in i2s_intr_handler_default()
249 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_intr_handler_default()
254 if ((status & I2S_LL_EVENT_TX_EOF) && p_i2s->tx) { in i2s_intr_handler_default()
255 i2s_hal_get_out_eof_des_addr(&(p_i2s->hal), &finish_desc); in i2s_intr_handler_default()
258 if (xQueueIsQueueFullFromISR(p_i2s->tx->queue)) { in i2s_intr_handler_default()
259 xQueueReceiveFromISR(p_i2s->tx->queue, &dummy, &tmp); in i2s_intr_handler_default()
261 if (p_i2s->i2s_queue) { in i2s_intr_handler_default()
263 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_intr_handler_default()
270 if (p_i2s->tx_desc_auto_clear == true) { in i2s_intr_handler_default()
271 memset((void *)(((lldesc_t *)finish_desc)->buf), 0, p_i2s->tx->buf_size); in i2s_intr_handler_default()
273 xQueueSendFromISR(p_i2s->tx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp); in i2s_intr_handler_default()
275 if (p_i2s->i2s_queue) { in i2s_intr_handler_default()
277 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_intr_handler_default()
282 if ((status & I2S_LL_EVENT_RX_EOF) && p_i2s->rx) { in i2s_intr_handler_default()
284 i2s_hal_get_in_eof_des_addr(&(p_i2s->hal), &finish_desc); in i2s_intr_handler_default()
286 if (xQueueIsQueueFullFromISR(p_i2s->rx->queue)) { in i2s_intr_handler_default()
287 xQueueReceiveFromISR(p_i2s->rx->queue, &dummy, &tmp); in i2s_intr_handler_default()
289 if (p_i2s->i2s_queue) { in i2s_intr_handler_default()
291 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_intr_handler_default()
295 xQueueSendFromISR(p_i2s->rx->queue, &(((lldesc_t *)finish_desc)->buf), &tmp); in i2s_intr_handler_default()
297 if (p_i2s->i2s_queue) { in i2s_intr_handler_default()
299 xQueueSendFromISR(p_i2s->i2s_queue, (void * )&i2s_event, &tmp); in i2s_intr_handler_default()
303 i2s_hal_clear_intr_status(&(p_i2s->hal), status); in i2s_intr_handler_default()
330 if ( p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_dma_intr_init()
333 …ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->tx_dma_chan), TAG, "Register tx dm… in i2s_dma_intr_init()
334 …ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->tx_dma_chan, trig), TAG, "Connect tx dma channel … in i2s_dma_intr_init()
337 gdma_register_tx_event_callbacks(p_i2s[i2s_num]->tx_dma_chan, &cb, p_i2s[i2s_num]); in i2s_dma_intr_init()
339 if ( p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_dma_intr_init()
342 …ESP_RETURN_ON_ERROR(gdma_new_channel(&dma_cfg, &p_i2s[i2s_num]->rx_dma_chan), TAG, "Register rx dm… in i2s_dma_intr_init()
343 …ESP_RETURN_ON_ERROR(gdma_connect(p_i2s[i2s_num]->rx_dma_chan, trig), TAG, "Connect rx dma channel … in i2s_dma_intr_init()
346 gdma_register_rx_event_callbacks(p_i2s[i2s_num]->rx_dma_chan, &cb, p_i2s[i2s_num]); in i2s_dma_intr_init()
350 …periph_signal[i2s_num].irq, intr_flag, i2s_intr_handler_default, p_i2s[i2s_num], &p_i2s[i2s_num]->… in i2s_dma_intr_init()
357 p_i2s[i2s_num]->tx->curr_ptr = NULL; in i2s_tx_reset()
358 p_i2s[i2s_num]->tx->rw_pos = 0; in i2s_tx_reset()
359 i2s_hal_tx_reset(&(p_i2s[i2s_num]->hal)); in i2s_tx_reset()
361 gdma_reset(p_i2s[i2s_num]->tx_dma_chan); in i2s_tx_reset()
363 i2s_hal_tx_reset_dma(&(p_i2s[i2s_num]->hal)); in i2s_tx_reset()
365 i2s_hal_tx_reset_fifo(&(p_i2s[i2s_num]->hal)); in i2s_tx_reset()
375 p_i2s[i2s_num]->rx->curr_ptr = NULL; in i2s_rx_reset()
376 p_i2s[i2s_num]->rx->rw_pos = 0; in i2s_rx_reset()
377 i2s_hal_rx_reset(&(p_i2s[i2s_num]->hal)); in i2s_rx_reset()
379 gdma_reset(p_i2s[i2s_num]->rx_dma_chan); in i2s_rx_reset()
381 i2s_hal_rx_reset_dma(&(p_i2s[i2s_num]->hal)); in i2s_rx_reset()
383 i2s_hal_rx_reset_fifo(&(p_i2s[i2s_num]->hal)); in i2s_rx_reset()
389 gdma_start(p_i2s[i2s_num]->tx_dma_chan, (uint32_t) p_i2s[i2s_num]->tx->desc[0]); in i2s_tx_start()
391 i2s_hal_tx_enable_dma(&(p_i2s[i2s_num]->hal)); in i2s_tx_start()
392 i2s_hal_tx_enable_intr(&(p_i2s[i2s_num]->hal)); in i2s_tx_start()
393 i2s_hal_tx_start_link(&(p_i2s[i2s_num]->hal), (uint32_t) p_i2s[i2s_num]->tx->desc[0]); in i2s_tx_start()
395 i2s_hal_tx_start(&(p_i2s[i2s_num]->hal)); in i2s_tx_start()
401 gdma_start(p_i2s[i2s_num]->rx_dma_chan, (uint32_t) p_i2s[i2s_num]->rx->desc[0]); in i2s_rx_start()
403 i2s_hal_rx_enable_dma(&(p_i2s[i2s_num]->hal)); in i2s_rx_start()
404 i2s_hal_rx_enable_intr(&(p_i2s[i2s_num]->hal)); in i2s_rx_start()
405 i2s_hal_rx_start_link(&(p_i2s[i2s_num]->hal), (uint32_t) p_i2s[i2s_num]->rx->desc[0]); in i2s_rx_start()
407 i2s_hal_rx_start(&(p_i2s[i2s_num]->hal)); in i2s_rx_start()
412 i2s_hal_tx_stop(&(p_i2s[i2s_num]->hal)); in i2s_tx_stop()
414 gdma_stop(p_i2s[i2s_num]->tx_dma_chan); in i2s_tx_stop()
416 i2s_hal_tx_stop_link(&(p_i2s[i2s_num]->hal)); in i2s_tx_stop()
417 i2s_hal_tx_disable_intr(&(p_i2s[i2s_num]->hal)); in i2s_tx_stop()
418 i2s_hal_tx_disable_dma(&(p_i2s[i2s_num]->hal)); in i2s_tx_stop()
424 i2s_hal_rx_stop(&(p_i2s[i2s_num]->hal)); in i2s_rx_stop()
426 gdma_stop(p_i2s[i2s_num]->rx_dma_chan); in i2s_rx_stop()
428 i2s_hal_rx_stop_link(&(p_i2s[i2s_num]->hal)); in i2s_rx_stop()
429 i2s_hal_rx_disable_intr(&(p_i2s[i2s_num]->hal)); in i2s_rx_stop()
430 i2s_hal_rx_disable_dma(&(p_i2s[i2s_num]->hal)); in i2s_rx_stop()
440 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_start()
444 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_start()
449 esp_intr_enable(p_i2s[i2s_num]->i2s_isr_handle); in i2s_start()
460 esp_intr_disable(p_i2s[i2s_num]->i2s_isr_handle); in i2s_stop()
462 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_stop()
465 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_stop()
469 i2s_hal_clear_intr_status(&(p_i2s[i2s_num]->hal), I2S_INTR_MAX); in i2s_stop()
480 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg; in i2s_get_buf_size()
484 uint32_t bytes_per_frame = bytes_per_sample * p_i2s[i2s_num]->active_slot; in i2s_get_buf_size()
485 …p_i2s[i2s_num]->dma_frame_num = (p_i2s[i2s_num]->dma_frame_num * bytes_per_frame > I2S_DMA_BUFFER_… in i2s_get_buf_size()
486 … I2S_DMA_BUFFER_MAX_SIZE / bytes_per_frame : p_i2s[i2s_num]->dma_frame_num; in i2s_get_buf_size()
487 return p_i2s[i2s_num]->dma_frame_num * bytes_per_frame; in i2s_get_buf_size()
493 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num; in i2s_delete_dma_buffer()
513 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num; in i2s_alloc_dma_buffer()
538 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_alloc_dma_buffer()
539 i2s_ll_rx_set_eof_num(p_i2s[i2s_num]->hal.dev, dma_obj->buf_size); in i2s_alloc_dma_buffer()
564 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_ARG, TAG, "I2S not initialized yet"); in i2s_destroy_dma_object()
595 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num; in i2s_create_dma_object()
672 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_calculate_adc_dac_clock()
673 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg; in i2s_calculate_adc_dac_clock()
680 clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ? in i2s_calculate_adc_dac_clock()
681 p_i2s[i2s_num]->fixed_mclk : clk_info->bclk * clk_info->bclk_div; in i2s_calculate_adc_dac_clock()
685 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_adc_dac_clock()
700 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_calculate_pdm_tx_clock()
709 clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ? in i2s_calculate_pdm_tx_clock()
710 p_i2s[i2s_num]->fixed_mclk : clk_info->bclk * clk_info->bclk_div; in i2s_calculate_pdm_tx_clock()
714 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_pdm_tx_clock()
729 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_calculate_pdm_rx_clock()
736 clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ? in i2s_calculate_pdm_rx_clock()
737 p_i2s[i2s_num]->fixed_mclk : clk_info->bclk * clk_info->bclk_div; in i2s_calculate_pdm_rx_clock()
741 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_pdm_rx_clock()
754 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_calculate_common_clock()
755 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg; in i2s_calculate_common_clock()
757 uint32_t slot_num = p_i2s[i2s_num]->total_slot < 2 ? 2 : p_i2s[i2s_num]->total_slot; in i2s_calculate_common_clock()
760 if (p_i2s[i2s_num]->role == I2S_ROLE_MASTER) { in i2s_calculate_common_clock()
771 clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk); in i2s_calculate_common_clock()
786 if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) { in i2s_calculate_clock()
794 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) { in i2s_calculate_clock()
796 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_calculate_clock()
801 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_calculate_clock()
822 i2s_dev_t *dev = p_i2s[0]->hal.dev; in i2s_dac_set_slot_legacy()
823 i2s_hal_slot_config_t *slot_cfg = &p_i2s[0]->slot_cfg; in i2s_dac_set_slot_legacy()
863 i2s_dev_t *dev = p_i2s[0]->hal.dev; in i2s_adc_set_slot_legacy()
864 i2s_hal_slot_config_t *slot_cfg = &p_i2s[0]->slot_cfg; in i2s_adc_set_slot_legacy()
898 … ESP_RETURN_ON_FALSE((p_i2s[i2s_num] != NULL), ESP_ERR_INVALID_STATE, TAG, "Not initialized yet"); in i2s_adc_enable()
899 …ESP_RETURN_ON_FALSE(((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) && (p_i2s[i2s_num]->dir &… in i2s_adc_enable()
911 … ESP_RETURN_ON_FALSE((p_i2s[i2s_num] != NULL), ESP_ERR_INVALID_STATE, TAG, "Not initialized yet"); in i2s_adc_disable()
912 …ESP_RETURN_ON_FALSE(((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) && (p_i2s[i2s_num]->dir &… in i2s_adc_disable()
915 i2s_hal_rx_stop(&(p_i2s[i2s_num]->hal)); in i2s_adc_disable()
926 …ESP_RETURN_ON_FALSE(p_i2s[i2s_num] == NULL, ESP_ERR_INVALID_STATE, TAG, "this i2s port is in use"); in i2s_check_cfg_validity()
965 bool is_tx_slave = p_i2s[i2s_num]->role == I2S_ROLE_SLAVE; in i2s_set_slot_legacy()
967 if (p_i2s[i2s_num]->dir == (I2S_DIR_TX_ | I2S_DIR_RX_)) { in i2s_set_slot_legacy()
968 i2s_ll_share_bck_ws(p_i2s[i2s_num]->hal.dev, true); in i2s_set_slot_legacy()
973 i2s_ll_share_bck_ws(p_i2s[i2s_num]->hal.dev, false); in i2s_set_slot_legacy()
975 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) { in i2s_set_slot_legacy()
976 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_slot_legacy()
977 …i2s_hal_std_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_… in i2s_set_slot_legacy()
979 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_slot_legacy()
980 …i2s_hal_std_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_… in i2s_set_slot_legacy()
984 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) { in i2s_set_slot_legacy()
986 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_slot_legacy()
987 …i2s_hal_pdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_… in i2s_set_slot_legacy()
991 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_slot_legacy()
992 …i2s_hal_pdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_… in i2s_set_slot_legacy()
998 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) { in i2s_set_slot_legacy()
999 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_slot_legacy()
1000 …i2s_hal_tdm_set_tx_slot(&(p_i2s[i2s_num]->hal), is_tx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_… in i2s_set_slot_legacy()
1002 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_slot_legacy()
1003 …i2s_hal_tdm_set_rx_slot(&(p_i2s[i2s_num]->hal), is_rx_slave, (i2s_hal_slot_config_t *)(&p_i2s[i2s_… in i2s_set_slot_legacy()
1008 else if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) { in i2s_set_slot_legacy()
1009 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_slot_legacy()
1012 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_slot_legacy()
1021 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_set_clock_legacy()
1024 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_clock_legacy()
1025 i2s_hal_set_tx_clock(&(p_i2s[i2s_num]->hal), &clk_info, clk_cfg->clk_src); in i2s_set_clock_legacy()
1027 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_clock_legacy()
1028 i2s_hal_set_rx_clock(&(p_i2s[i2s_num]->hal), &clk_info, clk_cfg->clk_src); in i2s_set_clock_legacy()
1035 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_get_clk()
1042 …ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_ARG, TAG, "I2S%d has not installed yet", i2s_n… in i2s_set_clk()
1045 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) { in i2s_set_clk()
1046 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY); in i2s_set_clk()
1048 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) { in i2s_set_clk()
1049 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY); in i2s_set_clk()
1055 i2s_clk_config_t *clk_cfg = &p_i2s[i2s_num]->clk_cfg; in i2s_set_clk()
1056 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg; in i2s_set_clk()
1066 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) { in i2s_set_clk()
1080 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) { in i2s_set_clk()
1085 …ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->total_slot >= (32 - __builtin_clz(slot_mask)), ESP_ERR_INVALID… in i2s_set_clk()
1086 … "The max channel number can't be greater than CH%"PRIu32, p_i2s[i2s_num]->total_slot); in i2s_set_clk()
1087 p_i2s[i2s_num]->active_slot = __builtin_popcount(slot_mask); in i2s_set_clk()
1091 p_i2s[i2s_num]->active_slot = (slot_cfg->slot_mode == I2S_SLOT_MODE_MONO) ? 1 : 2; in i2s_set_clk()
1098 bool need_realloc = buf_size != p_i2s[i2s_num]->last_buf_size; in i2s_set_clk()
1102 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_clk()
1103 p_i2s[i2s_num]->tx->buf_size = buf_size; in i2s_set_clk()
1104 ret = i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->tx); in i2s_set_clk()
1105 xQueueReset(p_i2s[i2s_num]->tx->queue); in i2s_set_clk()
1108 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_clk()
1109 p_i2s[i2s_num]->rx->buf_size = buf_size; in i2s_set_clk()
1110 ret = i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->rx); in i2s_set_clk()
1111 xQueueReset(p_i2s[i2s_num]->rx->queue); in i2s_set_clk()
1116 p_i2s[i2s_num]->last_buf_size = buf_size; in i2s_set_clk()
1121 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) { in i2s_set_clk()
1122 xSemaphoreGive(p_i2s[i2s_num]->tx->mux); in i2s_set_clk()
1124 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) { in i2s_set_clk()
1125 xSemaphoreGive(p_i2s[i2s_num]->rx->mux); in i2s_set_clk()
1134 i2s_hal_slot_config_t *slot_cfg = &p_i2s[i2s_num]->slot_cfg; in i2s_set_sample_rates()
1137 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) { in i2s_set_sample_rates()
1148 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_FAIL, TAG, "i2s has not installed yet"); in i2s_pcm_config()
1150 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) { in i2s_pcm_config()
1151 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY); in i2s_pcm_config()
1153 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) { in i2s_pcm_config()
1154 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY); in i2s_pcm_config()
1159 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_pcm_config()
1160 i2s_ll_tx_set_pcm_type(p_i2s[i2s_num]->hal.dev, pcm_cfg->pcm_type); in i2s_pcm_config()
1162 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_pcm_config()
1163 i2s_ll_rx_set_pcm_type(p_i2s[i2s_num]->hal.dev, pcm_cfg->pcm_type); in i2s_pcm_config()
1168 if (p_i2s[i2s_num]->dir & I2S_MODE_TX) { in i2s_pcm_config()
1169 xSemaphoreGive(p_i2s[i2s_num]->tx->mux); in i2s_pcm_config()
1171 if (p_i2s[i2s_num]->dir & I2S_MODE_RX) { in i2s_pcm_config()
1172 xSemaphoreGive(p_i2s[i2s_num]->rx->mux); in i2s_pcm_config()
1182 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_FAIL, TAG, "i2s has not installed yet"); in i2s_set_pdm_rx_down_sample()
1183 …ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM), ESP_ERR_INVALID_ARG, TAG, "i2s mo… in i2s_set_pdm_rx_down_sample()
1184 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY); in i2s_set_pdm_rx_down_sample()
1186 p_i2s[i2s_num]->clk_cfg.dn_sample_mode = downsample; in i2s_set_pdm_rx_down_sample()
1187 i2s_ll_rx_set_pdm_dsr(p_i2s[i2s_num]->hal.dev, downsample); in i2s_set_pdm_rx_down_sample()
1189 xSemaphoreGive(p_i2s[i2s_num]->rx->mux); in i2s_set_pdm_rx_down_sample()
1190 …return i2s_set_clk(i2s_num, p_i2s[i2s_num]->clk_cfg.sample_rate_hz, p_i2s[i2s_num]->slot_cfg.data_… in i2s_set_pdm_rx_down_sample()
1197 ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_FAIL, TAG, "i2s has not installed yet"); in i2s_set_pdm_tx_up_sample()
1198 …ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) && (p_i2s[i2s_num]->dir & I2S_DIR_… in i2s_set_pdm_tx_up_sample()
1200 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY); in i2s_set_pdm_tx_up_sample()
1202 p_i2s[i2s_num]->clk_cfg.up_sample_fp = upsample_cfg->fp; in i2s_set_pdm_tx_up_sample()
1203 p_i2s[i2s_num]->clk_cfg.up_sample_fs = upsample_cfg->fs; in i2s_set_pdm_tx_up_sample()
1204 i2s_ll_tx_set_pdm_fpfs(p_i2s[i2s_num]->hal.dev, upsample_cfg->fp, upsample_cfg->fs); in i2s_set_pdm_tx_up_sample()
1205 … i2s_ll_tx_set_pdm_over_sample_ratio(p_i2s[i2s_num]->hal.dev, upsample_cfg->fp / upsample_cfg->fs); in i2s_set_pdm_tx_up_sample()
1207 xSemaphoreGive(p_i2s[i2s_num]->tx->mux); in i2s_set_pdm_tx_up_sample()
1208 …return i2s_set_clk(i2s_num, p_i2s[i2s_num]->clk_cfg.sample_rate_hz, p_i2s[i2s_num]->slot_cfg.data_… in i2s_set_pdm_tx_up_sample()
1215 p_i2s[i2s_num]->last_buf_size = buf_size; in i2s_dma_object_init()
1217 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_dma_object_init()
1218 …ESP_RETURN_ON_ERROR(i2s_create_dma_object(i2s_num, &p_i2s[i2s_num]->tx), TAG, "I2S TX DMA object c… in i2s_dma_object_init()
1219 p_i2s[i2s_num]->tx->buf_size = buf_size; in i2s_dma_object_init()
1221 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_dma_object_init()
1222 …ESP_RETURN_ON_ERROR(i2s_create_dma_object(i2s_num, &p_i2s[i2s_num]->rx), TAG, "I2S RX DMA object c… in i2s_dma_object_init()
1223 p_i2s[i2s_num]->rx->buf_size = buf_size; in i2s_dma_object_init()
1231 p_i2s[i2s_num]->mode = I2S_COMM_MODE_STD; in i2s_mode_identify()
1234 p_i2s[i2s_num]->role = I2S_ROLE_MASTER; in i2s_mode_identify()
1236 p_i2s[i2s_num]->role = I2S_ROLE_SLAVE; in i2s_mode_identify()
1239 p_i2s[i2s_num]->dir |= I2S_DIR_TX_; in i2s_mode_identify()
1242 p_i2s[i2s_num]->dir |= I2S_DIR_RX_; in i2s_mode_identify()
1246 p_i2s[i2s_num]->mode = I2S_COMM_MODE_PDM; in i2s_mode_identify()
1252 p_i2s[i2s_num]->mode = I2S_COMM_MODE_TDM; in i2s_mode_identify()
1259 p_i2s[i2s_num]->mode = (i2s_comm_mode_t)I2S_COMM_MODE_ADC_DAC; in i2s_mode_identify()
1266 #define SLOT_CFG(m) p_i2s[i2s_num]->slot_cfg.m in i2s_config_transfer()
1267 #define CLK_CFG() p_i2s[i2s_num]->clk_cfg in i2s_config_transfer()
1269 p_i2s[i2s_num]->slot_cfg.data_bit_width = i2s_config->bits_per_sample; in i2s_config_transfer()
1270 …p_i2s[i2s_num]->slot_cfg.slot_bit_width = (int)i2s_config->bits_per_chan < (int)i2s_config->bits_p… in i2s_config_transfer()
1273 p_i2s[i2s_num]->slot_cfg.slot_mode = i2s_config->channel_format < I2S_CHANNEL_FMT_ONLY_RIGHT ? in i2s_config_transfer()
1278 p_i2s[i2s_num]->fixed_mclk = i2s_config->fixed_mclk; in i2s_config_transfer()
1279 p_i2s[i2s_num]->use_apll = false; in i2s_config_transfer()
1282 p_i2s[i2s_num]->use_apll = i2s_config->use_apll; in i2s_config_transfer()
1286 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) { in i2s_config_transfer()
1314 …p_i2s[i2s_num]->active_slot = (int)p_i2s[i2s_num]->slot_cfg.slot_mode == I2S_SLOT_MODE_MONO ? 1 : … in i2s_config_transfer()
1315 p_i2s[i2s_num]->total_slot = 2; in i2s_config_transfer()
1319 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) { in i2s_config_transfer()
1337 …p_i2s[i2s_num]->active_slot = (int)p_i2s[i2s_num]->slot_cfg.slot_mode == I2S_SLOT_MODE_MONO ? 1 : … in i2s_config_transfer()
1338 p_i2s[i2s_num]->total_slot = 2; in i2s_config_transfer()
1344 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) { in i2s_config_transfer()
1347 …p_i2s[i2s_num]->active_slot = (int)p_i2s[i2s_num]->slot_cfg.slot_mode == I2S_SLOT_MODE_MONO ? 1 : … in i2s_config_transfer()
1348 p_i2s[i2s_num]->total_slot = 2; in i2s_config_transfer()
1354 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) { in i2s_config_transfer()
1359 p_i2s[i2s_num]->slot_cfg.slot_mode = I2S_SLOT_MODE_STEREO; in i2s_config_transfer()
1369 SLOT_CFG(tdm).ws_width = p_i2s[i2s_num]->slot_cfg.slot_bit_width; in i2s_config_transfer()
1378 p_i2s[i2s_num]->active_slot = __builtin_popcount(SLOT_CFG(tdm).slot_mask); in i2s_config_transfer()
1381 … p_i2s[i2s_num]->total_slot = mx_slot < i2s_config->total_chan ? mx_slot : i2s_config->total_chan; in i2s_config_transfer()
1387 if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) { in i2s_config_transfer()
1388 p_i2s[i2s_num]->slot_cfg.slot_mode = (p_i2s[i2s_num]->dir & I2S_DIR_TX_) ? in i2s_config_transfer()
1390 p_i2s[i2s_num]->active_slot = (p_i2s[i2s_num]->dir & I2S_DIR_TX_) ? 2 : 1; in i2s_config_transfer()
1391 p_i2s[i2s_num]->total_slot = 2; in i2s_config_transfer()
1408 if (p_i2s[i2s_num]->use_apll) { in i2s_init_legacy()
1412 …ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock, 0, "i2s_driver", &p_i2s[i2s_num]->pm_lock), TAG, "… in i2s_init_legacy()
1416 if (p_i2s[i2s_num]->use_apll) { in i2s_init_legacy()
1422 if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_STD) { in i2s_init_legacy()
1423 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_init_legacy()
1424 i2s_hal_std_enable_tx_channel(&(p_i2s[i2s_num]->hal)); in i2s_init_legacy()
1426 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_init_legacy()
1427 i2s_hal_std_enable_rx_channel(&(p_i2s[i2s_num]->hal)); in i2s_init_legacy()
1431 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_PDM) { in i2s_init_legacy()
1433 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_init_legacy()
1434 i2s_hal_pdm_enable_tx_channel(&(p_i2s[i2s_num]->hal)); in i2s_init_legacy()
1438 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_init_legacy()
1439 i2s_hal_pdm_enable_rx_channel(&(p_i2s[i2s_num]->hal)); in i2s_init_legacy()
1445 else if (p_i2s[i2s_num]->mode == I2S_COMM_MODE_TDM) { in i2s_init_legacy()
1446 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_init_legacy()
1447 i2s_hal_tdm_enable_tx_channel(&(p_i2s[i2s_num]->hal)); in i2s_init_legacy()
1449 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_init_legacy()
1450 i2s_hal_tdm_enable_rx_channel(&(p_i2s[i2s_num]->hal)); in i2s_init_legacy()
1455 if ((int)p_i2s[i2s_num]->mode == I2S_COMM_MODE_ADC_DAC) { in i2s_init_legacy()
1456 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_init_legacy()
1459 i2s_ll_enable_builtin_adc(p_i2s[i2s_num]->hal.dev, true); in i2s_init_legacy()
1461 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_init_legacy()
1462 i2s_ll_enable_builtin_dac(p_i2s[i2s_num]->hal.dev, true); in i2s_init_legacy()
1466 i2s_ll_enable_builtin_adc(p_i2s[i2s_num]->hal.dev, false); in i2s_init_legacy()
1467 i2s_ll_enable_builtin_dac(p_i2s[i2s_num]->hal.dev, false); in i2s_init_legacy()
1475 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_init_legacy()
1476 …ESP_RETURN_ON_ERROR(i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->tx), TAG, "Allocate I2S dma tx… in i2s_init_legacy()
1478 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_init_legacy()
1479 …ESP_RETURN_ON_ERROR(i2s_realloc_dma_buffer(i2s_num, p_i2s[i2s_num]->rx), TAG, "Allocate I2S dma rx… in i2s_init_legacy()
1485 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_init_legacy()
1486 i2s_ll_tx_enable_clock(p_i2s[i2s_num]->hal.dev); in i2s_init_legacy()
1488 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_init_legacy()
1489 i2s_ll_rx_enable_clock(p_i2s[i2s_num]->hal.dev); in i2s_init_legacy()
1499 …ESP_RETURN_ON_FALSE(p_i2s[i2s_num], ESP_ERR_INVALID_STATE, TAG, "I2S port %d has not installed", i… in i2s_driver_uninstall()
1500 i2s_obj_t *obj = p_i2s[i2s_num]; in i2s_driver_uninstall()
1569 p_i2s[i2s_num] = NULL; in i2s_driver_uninstall()
1592 p_i2s[i2s_num] = i2s_obj; in i2s_driver_install()
1633 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->tx), ESP_ERR_INVALID_ARG, TAG, "TX mode is not enabled"); in i2s_write()
1634 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY); in i2s_write()
1636 esp_pm_lock_acquire(p_i2s[i2s_num]->pm_lock); in i2s_write()
1640 …if (p_i2s[i2s_num]->tx->rw_pos == p_i2s[i2s_num]->tx->buf_size || p_i2s[i2s_num]->tx->curr_ptr == … in i2s_write()
1641 …if (xQueueReceive(p_i2s[i2s_num]->tx->queue, &p_i2s[i2s_num]->tx->curr_ptr, ticks_to_wait) == pdFA… in i2s_write()
1644 p_i2s[i2s_num]->tx->rw_pos = 0; in i2s_write()
1646 …s: %d, buf_size: %d, curr_ptr: %d", size, p_i2s[i2s_num]->tx->rw_pos, p_i2s[i2s_num]->tx->buf_size… in i2s_write()
1647 data_ptr = (char *)p_i2s[i2s_num]->tx->curr_ptr; in i2s_write()
1648 data_ptr += p_i2s[i2s_num]->tx->rw_pos; in i2s_write()
1649 bytes_can_write = p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos; in i2s_write()
1656 p_i2s[i2s_num]->tx->rw_pos += bytes_can_write; in i2s_write()
1660 esp_pm_lock_release(p_i2s[i2s_num]->pm_lock); in i2s_write()
1662 xSemaphoreGive(p_i2s[i2s_num]->tx->mux); in i2s_write()
1678 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->tx), ESP_ERR_INVALID_ARG, TAG, "TX mode is not enabled"); in i2s_write_expand()
1699 xSemaphoreTake(p_i2s[i2s_num]->tx->mux, portMAX_DELAY); in i2s_write_expand()
1703 …if (p_i2s[i2s_num]->tx->rw_pos == p_i2s[i2s_num]->tx->buf_size || p_i2s[i2s_num]->tx->curr_ptr == … in i2s_write_expand()
1704 …if (xQueueReceive(p_i2s[i2s_num]->tx->queue, &p_i2s[i2s_num]->tx->curr_ptr, ticks_to_wait) == pdFA… in i2s_write_expand()
1707 p_i2s[i2s_num]->tx->rw_pos = 0; in i2s_write_expand()
1709 data_ptr = (char *)p_i2s[i2s_num]->tx->curr_ptr; in i2s_write_expand()
1710 data_ptr += p_i2s[i2s_num]->tx->rw_pos; in i2s_write_expand()
1711 bytes_can_write = p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos; in i2s_write_expand()
1725 p_i2s[i2s_num]->tx->rw_pos += bytes_can_write; in i2s_write_expand()
1727 xSemaphoreGive(p_i2s[i2s_num]->tx->mux); in i2s_write_expand()
1739 ESP_RETURN_ON_FALSE((p_i2s[i2s_num]->rx), ESP_ERR_INVALID_ARG, TAG, "RX mode is not enabled"); in i2s_read()
1740 xSemaphoreTake(p_i2s[i2s_num]->rx->mux, portMAX_DELAY); in i2s_read()
1742 esp_pm_lock_acquire(p_i2s[i2s_num]->pm_lock); in i2s_read()
1745 …if (p_i2s[i2s_num]->rx->rw_pos == p_i2s[i2s_num]->rx->buf_size || p_i2s[i2s_num]->rx->curr_ptr == … in i2s_read()
1746 …if (xQueueReceive(p_i2s[i2s_num]->rx->queue, &p_i2s[i2s_num]->rx->curr_ptr, ticks_to_wait) == pdFA… in i2s_read()
1749 p_i2s[i2s_num]->rx->rw_pos = 0; in i2s_read()
1751 data_ptr = (char *)p_i2s[i2s_num]->rx->curr_ptr; in i2s_read()
1752 data_ptr += p_i2s[i2s_num]->rx->rw_pos; in i2s_read()
1753 bytes_can_read = p_i2s[i2s_num]->rx->buf_size - p_i2s[i2s_num]->rx->rw_pos; in i2s_read()
1760 p_i2s[i2s_num]->rx->rw_pos += bytes_can_read; in i2s_read()
1764 esp_pm_lock_release(p_i2s[i2s_num]->pm_lock); in i2s_read()
1766 xSemaphoreGive(p_i2s[i2s_num]->rx->mux); in i2s_read()
1824 uint32_t buf_cnt = p_i2s[i2s_num]->dma_desc_num; in i2s_zero_dma_buffer()
1827 … if (p_i2s[i2s_num]->rx && p_i2s[i2s_num]->rx->buf != NULL && p_i2s[i2s_num]->rx->buf_size != 0) { in i2s_zero_dma_buffer()
1829 memset(p_i2s[i2s_num]->rx->buf[i], 0, p_i2s[i2s_num]->rx->buf_size); in i2s_zero_dma_buffer()
1834 … if (p_i2s[i2s_num]->tx && p_i2s[i2s_num]->tx->buf != NULL && p_i2s[i2s_num]->tx->buf_size != 0) { in i2s_zero_dma_buffer()
1836 int bytes_left = (p_i2s[i2s_num]->tx->buf_size - p_i2s[i2s_num]->tx->rw_pos) % 4; in i2s_zero_dma_buffer()
1843 memset(p_i2s[i2s_num]->tx->buf[i], 0, p_i2s[i2s_num]->tx->buf_size); in i2s_zero_dma_buffer()
1869 if (p_i2s[i2s_num]->role == I2S_ROLE_SLAVE) { in i2s_set_pin()
1871 if (p_i2s[i2s_num]->dir & I2S_DIR_RX_) { in i2s_set_pin()
1883 if (p_i2s[i2s_num]->dir & I2S_DIR_TX_) { in i2s_set_pin()