74     i2s_mclk_multiple_t     mclk_multiple;      /*!< The multiple of mclk to the sample rate */
120     i2s_mclk_multiple_t mclk_multiple; /*!< The multiple of I2S master clock(MCLK) to sample rate */
631 static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)  in i2s_config_source_clock()  argument
636         int div = (int)((SOC_APLL_MIN_HZ / mclk) + 1);  in i2s_config_source_clock()
637         /* apll_freq = mclk * div  in i2s_config_source_clock()
639          * when div = 0, the final mclk will be unpredictable  in i2s_config_source_clock()
642         uint32_t expt_freq = mclk * div;  in i2s_config_source_clock()
654         /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */  in i2s_config_source_clock()
669     /* For ADC/DAC mode, the built-in ADC/DAC is driven by 'mclk' instead of 'bclk'  in i2s_calculate_adc_dac_clock()
679 … If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk…  in i2s_calculate_adc_dac_clock()
680     clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?  in i2s_calculate_adc_dac_clock()
682     /* Calculate bclk_div = mclk / bclk */  in i2s_calculate_adc_dac_clock()
683     clk_info->bclk_div = clk_info->mclk / clk_info->bclk;  in i2s_calculate_adc_dac_clock()
685     clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);  in i2s_calculate_adc_dac_clock()
687     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;  in i2s_calculate_adc_dac_clock()
690 …ALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too …  in i2s_calculate_adc_dac_clock()
691 …>mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small, the mclk division exceed the…  in i2s_calculate_adc_dac_clock()
708 … If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk…  in i2s_calculate_pdm_tx_clock()
709     clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?  in i2s_calculate_pdm_tx_clock()
711     /* Calculate bclk_div = mclk / bclk */  in i2s_calculate_pdm_tx_clock()
712     clk_info->bclk_div = clk_info->mclk / clk_info->bclk;  in i2s_calculate_pdm_tx_clock()
714     clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);  in i2s_calculate_pdm_tx_clock()
716     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;  in i2s_calculate_pdm_tx_clock()
719 …ALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too …  in i2s_calculate_pdm_tx_clock()
720 …>mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small, the mclk division exceed the…  in i2s_calculate_pdm_tx_clock()
735 … If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk…  in i2s_calculate_pdm_rx_clock()
736     clk_info->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?  in i2s_calculate_pdm_rx_clock()
738     /* Calculate bclk_div = mclk / bclk */  in i2s_calculate_pdm_rx_clock()
739     clk_info->bclk_div = clk_info->mclk / clk_info->bclk;  in i2s_calculate_pdm_rx_clock()
741     clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);  in i2s_calculate_pdm_rx_clock()
743     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;  in i2s_calculate_pdm_rx_clock()
746 …ALSE(clk_info->sclk / (float)clk_info->mclk > 1.99, ESP_ERR_INVALID_ARG, TAG, "sample rate is too …  in i2s_calculate_pdm_rx_clock()
747 …>mclk_div < 256, ESP_ERR_INVALID_ARG, TAG, "sample rate is too small, the mclk division exceed the…  in i2s_calculate_pdm_rx_clock()
762         clk_info->mclk = rate * clk_cfg->mclk_multiple;  in i2s_calculate_common_clock()
763         clk_info->bclk_div = clk_info->mclk / clk_info->bclk;  in i2s_calculate_common_clock()
765         /* For slave mode, mclk >= bclk * 8, so fix bclk_div to 8 first */  in i2s_calculate_common_clock()
768         clk_info->mclk = clk_info->bclk * clk_info->bclk_div;  in i2s_calculate_common_clock()
771     clk_info->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_info->mclk);  in i2s_calculate_common_clock()
773     clk_info->mclk_div = clk_info->sclk / clk_info->mclk;  in i2s_calculate_common_clock()
776 …ESP_RETURN_ON_FALSE(clk_info->mclk <= clk_info->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is to…  in i2s_calculate_common_clock()
811     ESP_LOGD(TAG, "[sclk] %"PRIu32" [mclk] %"PRIu32" [mclk_div] %d [bclk] %"PRIu32" [bclk_div] %d",  in i2s_calculate_clock()
812 …           clk_info->sclk, clk_info->mclk, clk_info->mclk_div, clk_info->bclk, clk_info->bclk_div);  in i2s_calculate_clock()
1801 …     "ESP32 only support to set GPIO0/GPIO1/GPIO3 as mclk signal, error GPIO number:%d", gpio_num);  in i2s_check_set_mclk()
1817     ESP_LOGD(TAG, "I2S%d, MCLK output by GPIO%d", i2s_num, gpio_num);  in i2s_check_set_mclk()
1880         /* mclk only available in master mode */  in i2s_set_pin()
1881 …      ESP_RETURN_ON_ERROR(i2s_check_set_mclk(i2s_num, pin->mck_io_num), TAG, "mclk config failed");  in i2s_set_pin()