61 #define DPORT_CACHE_BIT(cpuid, regid) DPORT_ ## cpuid ## regid  argument
63 #define DPORT_CACHE_MASK(cpuid) (DPORT_CACHE_BIT(cpuid, _CACHE_MASK_OPSDRAM) | DPORT_CACHE_BIT(cpui…  argument
64 …          DPORT_CACHE_BIT(cpuid, _CACHE_MASK_DRAM1) | DPORT_CACHE_BIT(cpuid, _CACHE_MASK_IROM0) | \
65 …            DPORT_CACHE_BIT(cpuid, _CACHE_MASK_IRAM1) | DPORT_CACHE_BIT(cpuid, _CACHE_MASK_IRAM0) )
67 #define DPORT_CACHE_VAL(cpuid) (~(DPORT_CACHE_BIT(cpuid, _CACHE_MASK_DROM0) | \  argument
68                                         DPORT_CACHE_BIT(cpuid, _CACHE_MASK_DRAM1) | \
69                                         DPORT_CACHE_BIT(cpuid, _CACHE_MASK_IRAM0)))
71 #define DPORT_CACHE_GET_VAL(cpuid) (cpuid == 0) ? DPORT_CACHE_VAL(PRO) : DPORT_CACHE_VAL(APP)  argument
72 #define DPORT_CACHE_GET_MASK(cpuid) (cpuid == 0) ? DPORT_CACHE_MASK(PRO) : DPORT_CACHE_MASK(APP)  argument
78 void spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
79 void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
146     uint32_t cpuid = (uint32_t) arg;  in spi_flash_op_block_func()  local
156     spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);  in spi_flash_op_block_func()
174     const int cpuid = xPortGetCoreID();  in spi_flash_disable_interrupts_caches_and_other_cpu()  local
175     const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;  in spi_flash_disable_interrupts_caches_and_other_cpu()
179     s_flash_op_cpu = cpuid;  in spi_flash_disable_interrupts_caches_and_other_cpu()
215         assert(xPortGetCoreID() == cpuid);  in spi_flash_disable_interrupts_caches_and_other_cpu()
223     spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);  in spi_flash_disable_interrupts_caches_and_other_cpu()
229     const int cpuid = xPortGetCoreID();  in spi_flash_enable_interrupts_caches_and_other_cpu()  local
230     const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;  in spi_flash_enable_interrupts_caches_and_other_cpu()
233     assert(cpuid == s_flash_op_cpu);  in spi_flash_enable_interrupts_caches_and_other_cpu()
235     assert(!(xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED && cpuid != 0));  in spi_flash_enable_interrupts_caches_and_other_cpu()
240     spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);  in spi_flash_enable_interrupts_caches_and_other_cpu()
271     const uint32_t cpuid = xPortGetCoreID();  in spi_flash_disable_interrupts_caches_and_other_cpu_no_os()  local
272     const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;  in spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
279     spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);  in spi_flash_disable_interrupts_caches_and_other_cpu_no_os()
284     const uint32_t cpuid = xPortGetCoreID();  in spi_flash_enable_interrupts_caches_no_os()  local
287     spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);  in spi_flash_enable_interrupts_caches_no_os()
360 void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)  in spi_flash_disable_cache()  argument
364     const uint32_t cache_mask = DPORT_CACHE_GET_MASK(cpuid);  in spi_flash_disable_cache()
365     if (cpuid == 0) {  in spi_flash_disable_cache()
401 void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)  in spi_flash_restore_cache()  argument
404     const uint32_t cache_mask = DPORT_CACHE_GET_MASK(cpuid);  in spi_flash_restore_cache()
405     if (cpuid == 0) {  in spi_flash_restore_cache()
984 void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)  in spi_flash_enable_cache()  argument
987     uint32_t cache_value = DPORT_CACHE_GET_VAL(cpuid);  in spi_flash_enable_cache()
988     cache_value &= DPORT_CACHE_GET_MASK(cpuid);  in spi_flash_enable_cache()
991     spi_flash_restore_cache(cpuid, cache_value);  in spi_flash_enable_cache()