Lines Matching refs:be
12 …{IDF_TARGET_NAME} integrates two general purpose SPI controllers which can be used as slave nodes …
23 …{IDF_TARGET_NAME} integrates one general purpose SPI controller which can be used as slave node dr…
44 …asserting the CS line. Transactions are atomic, which means they can never be interrupted by anoth…
66 …ULL, the read phase will be skipped. If :cpp:member:`spi_slave_transaction_t::tx_buffer` is set to…
80 …If transactions will be longer than 32 bytes, allow a DMA channel 1 or 2 by setting the parameter …
84 …If transactions will be longer than 32 bytes, allow a DMA channel by setting the parameter ``dma_c…
86 …e latter two functions will be blocked until the Host has initiated and finished a transaction, ca…
94 …be transferred to or from a Device is read or written to a chunk of memory indicated by the :cpp:m…
96 …h drives the clock and CS lines. The actual length of the transmission can be read only after a tr…
98 …be sent and received. In this case, :cpp:member:`trans_len` is set to :cpp:member:`length` instead…
105 …t connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other …
107 …If at least one signal is routed through the GPIO matrix, then all signals will be routed through …
109 …outed to their dedicated IO_MUX pins or are not connected at all, the GPIO matrix will be bypassed.
151 …. All transactions must be handled by the CPU, which means that the transfers and responses are no…
153 As a solution, a Device's response rate can be doubled by using the functions :cpp:func:`spi_slave_…
155 …he Host when it is ready for a new transaction. A code example of this can be found in :example:`p…
163 The SPI slaves are designed to operate at up to {IDF_TARGET_MAX_FREQ} MHz. The data cannot be recog…
173 …The output delay of the MISO signal needs to be shorter than half of a clock cycle period so that …
186 …MISO pin is heavily loaded, the output delay will be longer, and the maximum allowed frequency wil…
188 …Exception: The frequency is allowed to be higher if the master has more tolerance for the MISO set…
196 1. If DMA is enabled, the rx buffer should be word-aligned (starting from a 32-bit boundary and hav…
198 …write lengths that are multiples of 4 bytes. The data with inappropriate lengths will be discarded.
202 … requires SPI modes 1 and 3. For SPI modes 0 and 2, the MISO signal has to be launched half a cloc…
212 The code example for Device/Host communication can be found in the :example:`peripherals/spi_slave`…