Lines Matching refs:R2
6 ULP coprocessor has 4 16-bit general purpose registers, labeled R0, R1, R2, R3. It also has an 8-bi…
55 MOVE R2, 0x1234
56 ST R2, R1, 0 // write value of R2 into the first array element,
59 ST R2, R1, 4 // write value of R2 into the second array element
63 ST R2, R1, 0 // write value of R2 into the third array element,
137 1: ADD R1, R2, R3 //R1 = R2 + R3
139 2: Add R1, R2, 0x1234 //R1 = R2 + 0x1234
142 Add R1, R2, value1 //R1 = R2 + value1
146 Add R1, R2, label //R1 = R2 + label
173 1: SUB R1, R2, R3 //R1 = R2 - R3
175 2: sub R1, R2, 0x1234 //R1 = R2 - 0x1234
178 SUB R1, R2, value1 //R1 = R2 - value1
180 SUB R1, R2, label //R1 = R2 - label
207 1: AND R1, R2, R3 //R1 = R2 & R3
209 2: AND R1, R2, 0x1234 //R1 = R2 & 0x1234
212 AND R1, R2, value1 //R1 = R2 & value1
215 AND R1, R2, label //R1 = R2 & label
242 1: OR R1, R2, R3 //R1 = R2 \| R3
244 2: OR R1, R2, 0x1234 //R1 = R2 \| 0x1234
247 OR R1, R2, value1 //R1 = R2 \| value1
250 OR R1, R2, label //R1 = R2 \|label
277 1: LSH R1, R2, R3 //R1 = R2 << R3
279 2: LSH R1, R2, 0x03 //R1 = R2 << 0x03
282 LSH R1, R2, value1 //R1 = R2 << value1
285 LSH R1, R2, label //R1 = R2 << label
312 1: RSH R1, R2, R3 //R1 = R2 >> R3
314 2: RSH R1, R2, 0x03 //R1 = R2 >> 0x03
317 RSH R1, R2, value1 //R1 = R2 >> value1
320 RSH R1, R2, label //R1 = R2 >> label
348 1: MOVE R1, R2 //R1 = R2
388 1: STL R1, R2, 0x12 //MEM[R2+0x12] = R1
395 MOVE R2, Addr1 // R2 = Addr1
396 STL R1, R2, offs // MEM[R2 + 0] = R1
400 STL R1, R2, 0x12,1 // MEM[R2+0x12] 0xxxxx4001
426 1: STH R1, R2, 0x12 //MEM[R2+0x12][31:16] = R1
433 MOVE R2, Addr1 // R2 = Addr1
434 STH R1, R2, offs // MEM[R2 + 0] = R1
438 STH R1, R2, 0x12, 1 //MEM[R2+0x12] 0x4001xxxx
493 STI R1, R2, 0x12 //MEM[R2+0x12][15:0] = R1
494 STI R1, R2, 0x12 //MEM[R2+0x12][31:16] = R1
502 MOVE R2, Addr1 // R2 = Addr1
503 STI R1, R2 // MEM[R2 + 0] = R1
505 STIx R1, R2 // MEM[R2 + 0] = R1
510 STI R1, R2, 1 //MEM[R2+0x12] 0xxxxx4001
511 STI R1, R2, 1 //MEM[R2+0x12] 0x40014001
536 1: ST32 R1, R2, 0x12, 0 //MEM[R2+0x12][31:0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]}
543 MOVE R2, Addr1 // R2 = Addr1
544 ST32 R1, R2, offs,1// MEM[R2 + 0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]}
572 STI32 R1, R2, 0 //MEM[R2+0x12][31:0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]}
573 STI32 R1, R2, 0 //MEM[R2+0x13][31:0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]}
580 MOVE R2, Addr1 // R2 = Addr1
582 STI32 R1, R2, 1// MEM[R2 + 0] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]}
584 ST32 R1, R2, 1// MEM[R2 + 1] = {PC[10:0],0[2:0],Label[1:0],Rsrc[15:0]}
614 1: LDL R1, R2, 0x12 //R1 = MEM[R2+0x12]
621 MOVE R2, Addr1 // R2 = Addr1 / 4 (address of label is converted into words)
622 LDL R1, R2, offs // R1 = MEM[R2 + 0]
651 1: LDH R1, R2, 0x12 //R1 = MEM[R2+0x12]
658 MOVE R2, Addr1 // R2 = Addr1 / 4 (address of label is converted into words)
659 LDH R1, R2, offs // R1 = MEM[R2 + 0]