Lines Matching full:1
23 uint32_t in_rst: 1;
24 uint32_t out_rst: 1;
25 uint32_t ahbm_fifo_rst: 1;
26 uint32_t ahbm_rst: 1;
27 uint32_t in_loop_test: 1;
28 uint32_t out_loop_test: 1;
29 uint32_t out_auto_wrback: 1;
30 uint32_t out_no_restart_clr: 1;
31 uint32_t out_eof_mode: 1;
32 uint32_t uart0_ce: 1;
33 uint32_t uart1_ce: 1;
34 uint32_t reserved11: 1;
35 uint32_t outdscr_burst_en: 1;
36 uint32_t indscr_burst_en: 1;
37 uint32_t out_data_burst_en: 1;
38 uint32_t mem_trans_en: 1;
39 uint32_t seper_en: 1;
40 uint32_t head_en: 1;
41 uint32_t crc_rec_en: 1;
42 uint32_t uart_idle_eof_en: 1;
43 uint32_t len_eof_en: 1;
44 uint32_t encode_crc_en: 1;
45 uint32_t clk_en: 1;
46 uint32_t uart_rx_brk_eof_en: 1;
53 uint32_t rx_start: 1;
54 uint32_t tx_start: 1;
55 uint32_t rx_hung: 1;
56 uint32_t tx_hung: 1;
57 uint32_t in_done: 1;
58 uint32_t in_suc_eof: 1;
59 uint32_t in_err_eof: 1;
60 uint32_t out_done: 1;
61 uint32_t out_eof: 1;
62 uint32_t in_dscr_err: 1;
63 uint32_t out_dscr_err: 1;
64 uint32_t in_dscr_empty: 1;
65 uint32_t outlink_eof_err: 1;
66 uint32_t out_total_eof: 1;
67 uint32_t send_s_q: 1;
68 uint32_t send_a_q: 1;
69 uint32_t dma_in_fifo_full_wm: 1;
76 uint32_t rx_start: 1;
77 uint32_t tx_start: 1;
78 uint32_t rx_hung: 1;
79 uint32_t tx_hung: 1;
80 uint32_t in_done: 1;
81 uint32_t in_suc_eof: 1;
82 uint32_t in_err_eof: 1;
83 uint32_t out_done: 1;
84 uint32_t out_eof: 1;
85 uint32_t in_dscr_err: 1;
86 uint32_t out_dscr_err: 1;
87 uint32_t in_dscr_empty: 1;
88 uint32_t outlink_eof_err: 1;
89 uint32_t out_total_eof: 1;
90 uint32_t send_s_q: 1;
91 uint32_t send_a_q: 1;
92 uint32_t dma_in_fifo_full_wm: 1;
99 uint32_t rx_start: 1;
100 uint32_t tx_start: 1;
101 uint32_t rx_hung: 1;
102 uint32_t tx_hung: 1;
103 uint32_t in_done: 1;
104 uint32_t in_suc_eof: 1;
105 uint32_t in_err_eof: 1;
106 uint32_t out_done: 1;
107 uint32_t out_eof: 1;
108 uint32_t in_dscr_err: 1;
109 uint32_t out_dscr_err: 1;
110 uint32_t in_dscr_empty: 1;
111 uint32_t outlink_eof_err: 1;
112 uint32_t out_total_eof: 1;
113 uint32_t send_s_q: 1;
114 uint32_t send_a_q: 1;
115 uint32_t dma_in_fifo_full_wm: 1;
122 uint32_t rx_start: 1;
123 uint32_t tx_start: 1;
124 uint32_t rx_hung: 1;
125 uint32_t tx_hung: 1;
126 uint32_t in_done: 1;
127 uint32_t in_suc_eof: 1;
128 uint32_t in_err_eof: 1;
129 uint32_t out_done: 1;
130 uint32_t out_eof: 1;
131 uint32_t in_dscr_err: 1;
132 uint32_t out_dscr_err: 1;
133 uint32_t in_dscr_empty: 1;
134 uint32_t outlink_eof_err: 1;
135 uint32_t out_total_eof: 1;
136 uint32_t send_s_q: 1;
137 uint32_t send_a_q: 1;
138 uint32_t dma_in_fifo_full_wm: 1;
145 uint32_t full: 1;
146 uint32_t empty: 1;
155 uint32_t fifo_push: 1;
162 uint32_t full: 1;
163 uint32_t empty: 1;
174 uint32_t fifo_pop: 1;
183 uint32_t stop: 1;
184 uint32_t start: 1;
185 uint32_t restart: 1;
186 uint32_t park: 1;
193 uint32_t auto_ret: 1;
195 uint32_t stop: 1;
196 uint32_t start: 1;
197 uint32_t restart: 1;
198 uint32_t park: 1;
204 uint32_t check_sum_en: 1;
205 uint32_t check_seq_en: 1;
206 uint32_t crc_disable: 1;
207 uint32_t save_head: 1;
208 uint32_t tx_check_sum_re: 1;
209 uint32_t tx_ack_num_re: 1;
210 uint32_t check_owner: 1;
211 uint32_t wait_sw_start: 1;
212 uint32_t sw_start: 1;
225 uint32_t reserved31: 1;
236 uint32_t reserved31: 1;
247 uint32_t reserved3: 1;
261 uint32_t tx_c0_esc_en: 1;
262 uint32_t tx_db_esc_en: 1;
263 uint32_t tx_11_esc_en: 1;
264 uint32_t tx_13_esc_en: 1;
265 uint32_t rx_c0_esc_en: 1;
266 uint32_t rx_db_esc_en: 1;
267 uint32_t rx_11_esc_en: 1;
268 uint32_t rx_13_esc_en: 1;
277 uint32_t txfifo_timeout_ena: 1;
280 uint32_t rxfifo_timeout_ena: 1;
290 uint32_t single_send_en: 1;
292 uint32_t always_send_en: 1;