Lines Matching refs:RwReg16
87 #define REG_SDHC1_BSR (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */
88 #define REG_SDHC1_BCR (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */
90 #define REG_SDHC1_TMR (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */
91 #define REG_SDHC1_CR (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */
102 #define REG_SDHC1_CCR (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */
105 #define REG_SDHC1_NISTR (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt S…
106 #define REG_SDHC1_EISTR (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt St…
107 #define REG_SDHC1_NISTER (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt S…
108 #define REG_SDHC1_EISTER (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt St…
109 #define REG_SDHC1_NISIER (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt S…
110 #define REG_SDHC1_EISIER (*(RwReg16*)0x4600003AUL) /**< \brief (SDHC1) Error Interrupt Si…
112 #define REG_SDHC1_HC2R (*(RwReg16*)0x4600003EUL) /**< \brief (SDHC1) Host Control 2 */
120 #define REG_SDHC1_PVR0 (*(RwReg16*)0x46000060UL) /**< \brief (SDHC1) Preset Value 0 */
121 #define REG_SDHC1_PVR1 (*(RwReg16*)0x46000062UL) /**< \brief (SDHC1) Preset Value 1 */
122 #define REG_SDHC1_PVR2 (*(RwReg16*)0x46000064UL) /**< \brief (SDHC1) Preset Value 2 */
123 #define REG_SDHC1_PVR3 (*(RwReg16*)0x46000066UL) /**< \brief (SDHC1) Preset Value 3 */
124 #define REG_SDHC1_PVR4 (*(RwReg16*)0x46000068UL) /**< \brief (SDHC1) Preset Value 4 */
125 #define REG_SDHC1_PVR5 (*(RwReg16*)0x4600006AUL) /**< \brief (SDHC1) Preset Value 5 */
126 #define REG_SDHC1_PVR6 (*(RwReg16*)0x4600006CUL) /**< \brief (SDHC1) Preset Value 6 */
127 #define REG_SDHC1_PVR7 (*(RwReg16*)0x4600006EUL) /**< \brief (SDHC1) Preset Value 7 */